dds.map.eqn

DDS的DSP实现

L3_unreg_res_node[17] = N9_cout[16] $ L8_unreg_res_node[11];


--N9_cs_buffer[15] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[15]
--operation mode is arithmetic

N9_cs_buffer[15] = N42_cs_buffer[9] $ N9_cout[14];

--N9_cout[15] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[15]
--operation mode is arithmetic

N9_cout[15] = CARRY(N42_cs_buffer[9] & N9_cout[14]);


--N9_cs_buffer[14] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[14]
--operation mode is arithmetic

N9_cs_buffer[14] = N42_cs_buffer[8] $ N9_cout[13];

--N9_cout[14] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[14]
--operation mode is arithmetic

N9_cout[14] = CARRY(N42_cs_buffer[8] & N9_cout[13]);


--N9_cs_buffer[13] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[13]
--operation mode is arithmetic

N9_cs_buffer[13] = N42_cs_buffer[7] $ N9_cout[12];

--N9_cout[13] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[13]
--operation mode is arithmetic

N9_cout[13] = CARRY(N42_cs_buffer[7] & N9_cout[12]);


--N9_cs_buffer[12] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]
--operation mode is arithmetic

N9_cs_buffer[12] = N42_cs_buffer[6] $ N9_cout[11];

--N9_cout[12] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[12]
--operation mode is arithmetic

N9_cout[12] = CARRY(N42_cs_buffer[6] & N9_cout[11]);


--N9_cs_buffer[11] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[11]
--operation mode is arithmetic

N9_cs_buffer[11] = N42_cs_buffer[5] $ N9_cout[10];

--N9_cout[11] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[11]
--operation mode is arithmetic

N9_cout[11] = CARRY(N42_cs_buffer[5] & N9_cout[10]);


--N9_cs_buffer[10] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[10]
--operation mode is arithmetic

N9_cs_buffer[10] = N42_cs_buffer[4] $ N9_cout[9];

--N9_cout[10] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[10]
--operation mode is arithmetic

N9_cout[10] = CARRY(N42_cs_buffer[4] & N9_cout[9]);


--N42_cs_buffer[10] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[10]
--operation mode is arithmetic

N42_cs_buffer[10] = N81_sout_node[8] $ L7_unreg_res_node[14] $ N42_cout[9];

--N42_cout[10] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[10]
--operation mode is arithmetic

N42_cout[10] = CARRY(N81_sout_node[8] & (L7_unreg_res_node[14] # N42_cout[9]) # !N81_sout_node[8] & L7_unreg_res_node[14] & N42_cout[9]);


--L8_unreg_res_node[11] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|unreg_res_node[11]
--operation mode is normal

L8_unreg_res_node[11] = L7_unreg_res_node[14] $ N81_sout_node[9] $ N42_cout[10];


--N81_sout_node[9] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|sout_node[9]
--operation mode is normal

N81_sout_node[9]_lut_out = N81_cout[8] $ T8L1 $ (G1_dataaint[9] & G1_databint[7]);
N81_sout_node[9] = DFFEA(N81_sout_node[9]_lut_out, clock, !sclrp, , , , );


--N81_sout_node[8] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|sout_node[8]
--operation mode is arithmetic

N81_sout_node[8]_lut_out = T21L8 $ T8L1 $ N81_cout[7];
N81_sout_node[8] = DFFEA(N81_sout_node[8]_lut_out, clock, !sclrp, , , , );

--N81_cout[8] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|cout[8]
--operation mode is arithmetic

N81_cout[8] = CARRY(T21L8 & (T8L1 # N81_cout[7]) # !T21L8 & T8L1 & N81_cout[7]);


--G1_databint[5] is SubDDS:SubDDSi|AltiMult:Product1i|databint[5]
--operation mode is normal

G1_databint[5]_lut_out = iAMPlifys[5] & !sclrp;
G1_databint[5] = DFFEA(G1_databint[5]_lut_out, clock, , , , , );


--G1_databint[6] is SubDDS:SubDDSi|AltiMult:Product1i|databint[6]
--operation mode is normal

G1_databint[6]_lut_out = iAMPlifys[6] & !sclrp;
G1_databint[6] = DFFEA(G1_databint[6]_lut_out, clock, , , , , );


--G1_dataaint[9] is SubDDS:SubDDSi|AltiMult:Product1i|dataaint[9]
--operation mode is normal

G1_dataaint[9]_lut_out = Q1_q[9] & !sclrp;
G1_dataaint[9] = DFFEA(G1_dataaint[9]_lut_out, clock, , , , , );


--G1_databint[7] is SubDDS:SubDDSi|AltiMult:Product1i|databint[7]
--operation mode is normal

G1_databint[7]_lut_out = iAMPlifys[7] & !sclrp;
G1_databint[7] = DFFEA(G1_databint[7]_lut_out, clock, , , , , );


--T8L1 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:$00046|out_bit[0]~0
--operation mode is normal

T8L1 = G1_dataaint[9] & !G1_databint[7] & (G1_databint[5] # G1_databint[6]) # !G1_dataaint[9] & G1_databint[7] & (!G1_databint[6] # !G1_databint[5]);


--N12_cs_buffer[13] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[13]
--operation mode is arithmetic

N12_cs_buffer[13] = N51_sout_node[11] $ N21_sout_node[12] $ N12_cout[12];

--N12_cout[13] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[13]
--operation mode is arithmetic

N12_cout[13] = CARRY(N51_sout_node[11] & (N21_sout_node[12] # N12_cout[12]) # !N51_sout_node[11] & N21_sout_node[12] & N12_cout[12]);


--L7_unreg_res_node[14] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|unreg_res_node[14]
--operation mode is normal

L7_unreg_res_node[14] = N21_sout_node[12] $ N51_sout_node[12] $ N12_cout[13];


--N42_cs_buffer[9] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]
--operation mode is arithmetic

N42_cs_buffer[9] = N81_sout_node[7] $ N12_cs_buffer[13] $ N42_cout[8];

--N42_cout[9] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[9]
--operation mode is arithmetic

N42_cout[9] = CARRY(N81_sout_node[7] & (N12_cs_buffer[13] # N42_cout[8]) # !N81_sout_node[7] & N12_cs_buffer[13] & N42_cout[8]);


--N42_cs_buffer[8] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]
--operation mode is arithmetic

N42_cs_buffer[8] = N81_sout_node[6] $ N12_cs_buffer[12] $ N42_cout[7];

--N42_cout[8] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[8]
--operation mode is arithmetic

N42_cout[8] = CARRY(N81_sout_node[6] & (N12_cs_buffer[12] # N42_cout[7]) # !N81_sout_node[6] & N12_cs_buffer[12] & N42_cout[7]);


--N42_cs_buffer[7] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]
--operation mode is arithmetic

N42_cs_buffer[7] = N81_sout_node[5] $ N12_cs_buffer[11] $ N42_cout[6];

--N42_cout[7] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[7]
--operation mode is arithmetic

N42_cout[7] = CARRY(N81_sout_node[5] & (N12_cs_buffer[11] # N42_cout[6]) # !N81_sout_node[5] & N12_cs_buffer[11] & N42_cout[6]);


--N42_cs_buffer[6] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]
--operation mode is arithmetic

N42_cs_buffer[6] = N81_sout_node[4] $ N12_cs_buffer[10] $ N42_cout[5];

--N42_cout[6] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[6]
--operation mode is arithmetic

N42_cout[6] = CARRY(N81_sout_node[4] & (N12_cs_buffer[10] # N42_cout[5]) # !N81_sout_node[4] & N12_cs_buffer[10] & N42_cout[5]);


--N42_cs_buffer[5] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

N42_cs_buffer[5] = N81_sout_node[3] $ N12_cs_buffer[9] $ N42_cout[4];

--N42_cout[5] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

N42_cout[5] = CARRY(N81_sout_node[3] & (N12_cs_buffer[9] # N42_cout[4]) # !N81_sout_node[3] & N12_cs_buffer[9] & N42_cout[4]);


--N42_cs_buffer[4] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

N42_cs_buffer[4] = N81_sout_node[2] $ N12_cs_buffer[8] $ N42_cout[3];

--N42_cout[4] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

N42_cout[4] = CARRY(N81_sout_node[2] & (N12_cs_buffer[8] # N42_cout[3]) # !N81_sout_node[2] & N12_cs_buffer[8] & N42_cout[3]);


--N9_cs_buffer[9] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]
--operation mode is arithmetic

N9_cs_buffer[9] = N42_cs_buffer[3] $ N9_cout[8];

--N9_cout[9] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[9]
--operation mode is arithmetic

N9_cout[9] = CARRY(N42_cs_buffer[3] & N9_cout[8]);


--Q1_q[9] is SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[9]
Q1_q[9]_write_address = WR_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[9]_read_address = RD_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[9] = MEMORY_SEGMENT(, , , , , , , , Q1_q[9]_write_address, Q1_q[9]_read_address);


--N51_sout_node[12] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|sout_node[12]
--operation mode is normal

N51_sout_node[12]_lut_out = T6L1 $ T4L1 $ N51_cout[11];
N51_sout_node[12] = DFFEA(N51_sout_node[12]_lut_out, clock, !sclrp, , , , );


--N51_sout_node[11] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|sout_node[11]
--operation mode is arithmetic

N51_sout_node[11]_lut_out = T6L1 $ T4L1 $ N51_cout[10];
N51_sout_node[11] = DFFEA(N51_sout_node[11]_lut_out, clock, !sclrp, , , , );

--N51_cout[11] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cout[11]
--operation mode is arithmetic

N51_cout[11] = CARRY(T6L1 & (T4L1 # N51_cout[10]) # !T6L1 & T4L1 & N51_cout[10]);


--G1_databint[2] is SubDDS:SubDDSi|AltiMult:Product1i|databint[2]
--operation mode is normal

G1_databint[2]_lut_out = iAMPlifys[2] & !sclrp;
G1_databint[2] = DFFEA(G1_databint[2]_lut_out, clock, , , , , );


--G1_databint[1] is SubDDS:SubDDSi|AltiMult:Product1i|databint[1]
--operation mode is normal

G1_databint[1]_lut_out = iAMPlifys[1] & !sclrp;
G1_databint[1] = DFFEA(G1_databint[1]_lut_out, clock, , , , , );


--G1_databint[3] is SubDDS:SubDDSi|AltiMult:Product1i|databint[3]
--operation mode is normal

G1_databint[3]_lut_out = iAMPlifys[3] & !sclrp;
G1_databint[3] = DFFEA(G1_databint[3]_lut_out, clock, , , , , );


--T4L1 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:$00038|out_bit[0]~0
--operation mode is normal