dds.vqm

DDS的DSP实现

wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[5] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[6] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[7] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[8] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[9] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[10] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[11] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[12] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[13] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[14] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[15] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[16] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|unreg_res_node[17] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[16] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[15] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[14] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[13] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[12] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[11] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] ;
wire [18:0] \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout ;
wire [16:0] \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout ;
wire [12:0] \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|sout_node ;
wire [17:0] \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer ;
wire [31:0] \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|unreg_res_node ;
wire [9:0] \SubDDS:SubDDSi|AltiMult:Product1i|dataaint ;
wire [14:0] \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|unreg_res_node ;
wire [31:0] \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout ;
wire [14:0] \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout ;
wire [17:0] \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|unreg_res_node ;
wire [18:0] \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer ;
wire [16:0] \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer ;
wire [8:0] \SubDDS:SubDDSi|AltiMult:Product1i|databint ;
wire [31:0] \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer ;
wire [14:0] \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer ;
wire [12:0] \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout ;
wire [17:0] \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cout ;
wire [12:0] \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|cout ;
wire [17:0] \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cout ;
wire [17:0] \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|unreg_res_node ;
wire [12:0] \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|sout_node ;
wire [17:0] \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer ;
wire [16:0] \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|unreg_res_node ;
wire [12:0] \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|sout_node ;
wire [18:0] \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|unreg_res_node ;
wire [12:0] \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cout ;
wire [9:0] \SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q ;

wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|__ALT_INV__unreg_res_node[17] ;

wire gnd;
wire vcc;

assign gnd = 1'b0;
assign vcc = 1'b1;

assign \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|__ALT_INV__unreg_res_node[17]  = ~ \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|unreg_res_node[17] ;

flex10ke_io \sclrp~I (
	.dataout(\sclrp~dataout ),
	.padio(sclrp));
defparam \sclrp~I .operation_mode = "input";
defparam \sclrp~I .reg_source_mode = "none";
defparam \sclrp~I .feedback_mode = "from_pin";

flex10ke_io \iAMPlifys[7]~I (
	.dataout(\iAMPlifys[7]~dataout ),
	.padio(iAMPlifys[7]));
defparam \iAMPlifys[7]~I .operation_mode = "input";
defparam \iAMPlifys[7]~I .reg_source_mode = "none";
defparam \iAMPlifys[7]~I .feedback_mode = "from_pin";

flex10ke_io \clock~I (
	.dataout(\clock~dataout ),
	.padio(clock));
defparam \clock~I .operation_mode = "input";
defparam \clock~I .reg_source_mode = "none";
defparam \clock~I .feedback_mode = "from_pin";

flex10ke_lcell \SubDDS:SubDDSi|AltiMult:Product1i|databint[7]~I (
	.datac(\sclrp~dataout ),
	.datad(\iAMPlifys[7]~dataout ),
	.clk(\clock~dataout ),
	.regout(\SubDDS:SubDDSi|AltiMult:Product1i|databint[7] ));
defparam \SubDDS:SubDDSi|AltiMult:Product1i|databint[7]~I .operation_mode = "normal";
defparam \SubDDS:SubDDSi|AltiMult:Product1i|databint[7]~I .packed_mode = "false";
defparam \SubDDS:SubDDSi|AltiMult:Product1i|databint[7]~I .lut_mask = "0F00";
defparam \SubDDS:SubDDSi|AltiMult:Product1i|databint[7]~I .clock_enable_mode = "false";
defparam \SubDDS:SubDDSi|AltiMult:Product1i|databint[7]~I .output_mode = "reg_only";

flex10ke_io \iFREQWORDs[7]~I (
	.dataout(\iFREQWORDs[7]~dataout ),
	.padio(iFREQWORDs[7]));
defparam \iFREQWORDs[7]~I .operation_mode = "input";
defparam \iFREQWORDs[7]~I .reg_source_mode = "none";
defparam \iFREQWORDs[7]~I .feedback_mode = "from_pin";

flex10ke_lcell \SubDDS:SubDDSi|SDelay:Delayi|result[22]~reg0_I (
	.datac(\sclrp~dataout ),
	.datad(\iFREQWORDs[7]~dataout ),
	.clk(\clock~dataout ),
	.regout(\SubDDS:SubDDSi|SDelay:Delayi|result[22]~reg0 ));
defparam \SubDDS:SubDDSi|SDelay:Delayi|result[22]~reg0_I .operation_mode = "normal";
defparam \SubDDS:SubDDSi|SDelay:Delayi|result[22]~reg0_I .packed_mode = "false";
defparam \SubDDS:SubDDSi|SDelay:Delayi|result[22]~reg0_I .lut_mask = "0F00";
defparam \SubDDS:SubDDSi|SDelay:Delayi|result[22]~reg0_I .clock_enable_mode = "false";
defparam \SubDDS:SubDDSi|SDelay:Delayi|result[22]~reg0_I .output_mode = "reg_only";

flex10ke_io \iFREQWORDs[6]~I (
	.dataout(\iFREQWORDs[6]~