dds.vqm

DDS的DSP实现

wire \SubDDS:SubDDSi|SAdderSub:u9|result[19]~reg0 ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[4] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|result[20]~reg0 ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[5] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|result[21]~reg0 ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[6] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|result[22]~reg0 ;
wire \SubDDS:SubDDSi|SAdderSub:u9|result[31]~reg0 ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[7] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|result[23]~reg0 ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[8] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[9] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|result[24]~reg0 ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[9] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|result[25]~reg0 ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[10] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[11] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|result[26]~reg0 ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[11] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[12] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|result[27]~reg0 ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[12] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[13] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|result[28]~reg0 ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[13] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[14] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|result[29]~reg0 ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[14] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[15] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|result[30]~reg0 ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[15] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|unreg_res_node[16] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|i108~0 ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[15] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[16] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[17] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[18] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[19] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[20] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[21] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[22] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[22] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[23] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[23] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[24] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[24] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[25] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[25] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[26] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[26] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[27] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[27] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[28] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[28] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[29] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[29] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[30] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[30] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|unreg_res_node[31] ;
wire \SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[9] ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|dataaint[9] ;
wire \iAMPlifys[6]~dataout ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|databint[6] ;
wire \iAMPlifys[5]~dataout ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|databint[5] ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:$00046|out_bit[0]~0 ;
wire \SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[8] ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|dataaint[8] ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_last_mod|left_bit[7]~7 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[8]~117 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|out_bit[8]~154 ;
wire \SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[7] ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|dataaint[7] ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_last_mod|left_bit[6]~6 ;
wire \SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[6] ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|dataaint[6] ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_last_mod|left_bit[5]~5 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[7]~118 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|out_bit[7]~155 ;
wire \SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[5] ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|dataaint[5] ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_last_mod|left_bit[4]~4 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[6]~119 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|out_bit[6]~156 ;
wire \SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[4] ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|dataaint[4] ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_last_mod|left_bit[3]~3 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[5]~120 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|out_bit[5]~157 ;
wire \SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[3] ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|dataaint[3] ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_last_mod|left_bit[2]~2 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[4]~121 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|out_bit[4]~158 ;
wire \SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[2] ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|dataaint[2] ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_last_mod|left_bit[1]~1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[3]~122 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|out_bit[3]~159 ;
wire \SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[1] ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|dataaint[1] ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_last_mod|left_bit[0]~0 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[2]~123 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|out_bit[2]~160 ;
wire \SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[0] ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|dataaint[0] ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:$00048|left_bit[0]~0 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[1]~124 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|out_bit[1]~161 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|cout[0] ;