dds.fit.eqn

DDS的DSP实现

N51_sout_node[7]_lut_out = T41L9 $ T51L7 $ N51_cout[6];
N51_sout_node[7] = DFFEA(N51_sout_node[7]_lut_out, GLOBAL(clock), !GLOBAL(sclrp), , , , );

--N51_cout[7] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cout[7] at LC2_C5
--operation mode is arithmetic

N51_cout[7] = CARRY(T41L9 & !T51L7 & N51_cout[6] # !T41L9 & (N51_cout[6] # !T51L7));


--G1_dataaint[2] is SubDDS:SubDDSi|AltiMult:Product1i|dataaint[2] at LC1_C20
--operation mode is normal

G1_dataaint[2]_lut_out = !sclrp & Q1_q[2];
G1_dataaint[2] = DFFEA(G1_dataaint[2]_lut_out, GLOBAL(clock), , , , , );


--T21L2 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_last_mod|left_bit[1]~1 at LC3_C20
--operation mode is normal

T21L2 = G1_databint[7] & G1_dataaint[2];


--N81_sout_node[1] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|sout_node[1] at LC5_C20
--operation mode is arithmetic

N81_sout_node[1]_lut_out = T21L1 $ T61L3 $ !N81_cout[0];
N81_sout_node[1] = DFFEA(N81_sout_node[1]_lut_out, GLOBAL(clock), !GLOBAL(sclrp), , , , );

--N81_cout[1] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|cout[1] at LC5_C20
--operation mode is arithmetic

N81_cout[1] = CARRY(T21L1 & (N81_cout[0] # !T61L3) # !T21L1 & !T61L3 & N81_cout[0]);


--N51_sout_node[6] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|sout_node[6] at LC1_C5
--operation mode is arithmetic

N51_sout_node[6]_lut_out = T41L8 $ T51L6 $ N51_cout[5];
N51_sout_node[6] = DFFEA(N51_sout_node[6]_lut_out, GLOBAL(clock), !GLOBAL(sclrp), , , , );

--N51_cout[6] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cout[6] at LC1_C5
--operation mode is arithmetic

N51_cout[6] = CARRY(T41L8 & !T51L6 & N51_cout[5] # !T41L8 & (N51_cout[5] # !T51L6));


--N12_cs_buffer[7] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] at LC1_C10
--operation mode is arithmetic

N12_cs_buffer[7] = N21_sout_node[9] $ N51_sout_node[5] $ N12_cout[6];

--N12_cout[7] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[7] at LC1_C10
--operation mode is arithmetic

N12_cout[7] = CARRY(N21_sout_node[9] & (N51_sout_node[5] # N12_cout[6]) # !N21_sout_node[9] & N51_sout_node[5] & N12_cout[6]);


--N42_cs_buffer[2] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] at LC5_C33
--operation mode is arithmetic

N42_cs_buffer[2] = N12_cs_buffer[6] $ N81_sout_node[0] $ N42_cout[1];

--N42_cout[2] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[2] at LC5_C33
--operation mode is arithmetic

N42_cout[2] = CARRY(N12_cs_buffer[6] & (N81_sout_node[0] # N42_cout[1]) # !N12_cs_buffer[6] & N81_sout_node[0] & N42_cout[1]);


--N9_cs_buffer[7] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] at LC3_C29
--operation mode is arithmetic

N9_cs_buffer[7] = N42_cs_buffer[1] $ N9_cout[6];

--N9_cout[7] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[7] at LC3_C29
--operation mode is arithmetic

N9_cout[7] = CARRY(N42_cs_buffer[1] & N9_cout[6]);


--Q1_q[7] is SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[7] at EC9_E
Q1_q[7]_write_address = WR_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[7]_read_address = RD_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[7] = MEMORY_SEGMENT(, , , , , , , , Q1_q[7]_write_address, Q1_q[7]_read_address);


--N72_cs_buffer[7] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] at LC4_F13
--operation mode is arithmetic

N72_cs_buffer[7] = H1L9Q $ E1L8Q $ N72_cout[6];

--N72_cout[7] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[7] at LC4_F13
--operation mode is arithmetic

N72_cout[7] = CARRY(H1L9Q & (E1L8Q # N72_cout[6]) # !H1L9Q & E1L8Q & N72_cout[6]);


--N72_cs_buffer[8] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] at LC5_F13
--operation mode is arithmetic

N72_cs_buffer[8] = H1L01Q $ N72_cout[7];

--N72_cout[8] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[8] at LC5_F13
--operation mode is arithmetic

N72_cout[8] = CARRY(H1L01Q & N72_cout[7]);


--N72_cs_buffer[9] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[9] at LC6_F13
--operation mode is arithmetic

N72_cs_buffer[9] = H1L11Q $ N72_cout[8];

--N72_cout[9] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[9] at LC6_F13
--operation mode is arithmetic

N72_cout[9] = CARRY(H1L11Q & N72_cout[8]);


--N72_cs_buffer[10] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] at LC7_F13
--operation mode is arithmetic

N72_cs_buffer[10] = H1L21Q $ N72_cout[9];

--N72_cout[10] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[10] at LC7_F13
--operation mode is arithmetic

N72_cout[10] = CARRY(H1L21Q & N72_cout[9]);


--N72_cs_buffer[11] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[11] at LC8_F13
--operation mode is arithmetic

N72_cs_buffer[11] = H1L31Q $ N72_cout[10];

--N72_cout[11] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[11] at LC8_F13
--operation mode is arithmetic

N72_cout[11] = CARRY(H1L31Q & N72_cout[10]);


--N72_cs_buffer[12] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[12] at LC1_F15
--operation mode is arithmetic

N72_cs_buffer[12] = H1L41Q $ N72_cout[11];

--N72_cout[12] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[12] at LC1_F15
--operation mode is arithmetic

N72_cout[12] = CARRY(H1L41Q & N72_cout[11]);


--N72_cs_buffer[13] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[13] at LC2_F15
--operation mode is arithmetic

N72_cs_buffer[13] = H1L51Q $ N72_cout[12];

--N72_cout[13] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[13] at LC2_F15
--operation mode is arithmetic

N72_cout[13] = CARRY(H1L51Q & N72_cout[12]);


--N72_cs_buffer[14] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[14] at LC3_F15
--operation mode is arithmetic

N72_cs_buffer[14] = H1L61Q $ N72_cout[13];

--N72_cout[14] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[14] at LC3_F15
--operation mode is arithmetic

N72_cout[14] = CARRY(H1L61Q & N72_cout[13]);


--N72_cs_buffer[15] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[15] at LC4_F15
--operation mode is arithmetic

N72_cs_buffer[15] = H1L71Q $ N72_cout[14];

--N72_cout[15] is SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[15] at LC4_F15
--operation mode is arithmetic

N72_cout[15] = CARRY(H1L71Q & N72_cout[14]);


--N21_sout_node[9] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|sout_node[9] at LC4_C14
--operation mode is arithmetic

N21_sout_node[9]_lut_out = N21_cout[8] $ (T11L41 # T2L1);
N21_sout_node[9] = DFFEA(N21_sout_node[9]_lut_out, GLOBAL(clock), !GLOBAL(sclrp), , , , );

--N21_cout[9] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[9] at LC4_C14
--operation mode is arithmetic

N21_cout[9] = CARRY(N21_cout[8] & (T11L41 # T2L1));


--Q1_q[6] is SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[6] at EC2_F
Q1_q[6]_write_address = WR_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[6]_read_address = RD_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[6] = MEMORY_SEGMENT(, , , , , , , , Q1_q[6]_write_address, Q1_q[6]_read_address);


--Q1_q[5] is SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[5] at EC10_F
Q1_q[5]_write_address = WR_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[5]_read_address = RD_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[5] = MEMORY_SEGMENT(, , , , , , , , Q1_q[5]_write_address, Q1_q[5]_read_address);


--Q1_q[4] is SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[4] at EC1_F
Q1_q[4]_write_address = WR_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[4]_read_address = RD_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[4] = MEMORY_SEGMENT(, , , , , , , , Q1_q[4]_write_address, Q1_q[4]_read_address);


--Q1_q[3] is SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[3] at EC9_F
Q1_q[3]_write_address = WR_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[3]_read_address = RD_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[3] = MEMORY_SEGMENT(, , , , , , , , Q1_q[3]_write_address, Q1_q[3]_read_address);


--Q1_q[2] is SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[2] at EC10_C
Q1_q[2]_write_address = WR_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[2]_read_address = RD_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[2] = MEMORY_SEGMENT(, , , , , , , , Q1_q[2]_write_address, Q1_q[2]_read_address);


--T61L9 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|out_bit[8]~154 at LC8_C22
--operation mode is normal

T61L9 = (G1_databint[7] & (G1_dataaint[9] # G1_databint[6] $ !G1_databint[5]) # !G1_databint[7] & (G1_databint[6] $ !G1_databint[5] # !G1_dataaint[9])) & CASCADE(T61L81);


--T61L81 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[8]~117 at LC7_C22
--operation mode is normal

T61L81 = G1_databint[7] & (G1_databint[6] # G1_databint[5] # G1_dataaint[8]) # !G1_databint[7] & (!G1_dataaint[8] # !G1_databint[5] # !G1_databint[6]);


--H1L8Q is SubDDS:SubDDSi|SAdderSub:u9|result[21]~reg0 at LC1_F12
--operation mode is normal

H1L8Q_lut_out = !sclrp & N72_cs_buffer[6];
H1L8Q = DFFEA(H1L8Q_lut_out, GLOBAL(clock), , , , , );


--H1L1 is SubDDS:SubDDSi|SAdderSub:u9|i108~0 at LC8_F15
--operation mode is normal

H1L1 = !sclrp & L9_unreg_res_node[16];


--T61L8 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|out_bit[7]~155 at LC7_C6
--operation mode is normal

T61L8 = (G1_databint[6] & (G1_databint[5] # G1_databint[7] $ !G1_dataaint[8]) # !G1_databint[6] & (G1_databint[7] $ !G1_dataaint[8] # !G1_databint[5])) & CASCADE(T61L71);


--T61L71 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[7]~118 at LC6_C6
--operation mode is normal

T61L71 = G1_databint[7] & (G1_databint[6] # G1_databint[5] # G1_dataaint[7]) # !G1_databint[7] & (!G1_dataaint[7] # !G1_databint[5] # !G1_databint[6]);


--T61L7 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|out_bit[6]~156 at LC4_C25
--operation mode is normal

T61L7 = (G1_databint[6] & (G1_data