dds.fit.eqn

DDS的DSP实现

--N12_cs_buffer[9] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[9] at LC3_C10
--operation mode is arithmetic

N12_cs_buffer[9] = N21_sout_node[11] $ N51_sout_node[7] $ N12_cout[8];

--N12_cout[9] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[9] at LC3_C10
--operation mode is arithmetic

N12_cout[9] = CARRY(N21_sout_node[11] & (N51_sout_node[7] # N12_cout[8]) # !N21_sout_node[11] & N51_sout_node[7] & N12_cout[8]);


--N81_sout_node[2] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|sout_node[2] at LC6_C20
--operation mode is arithmetic

N81_sout_node[2]_lut_out = T21L2 $ T61L4 $ !N81_cout[1];
N81_sout_node[2] = DFFEA(N81_sout_node[2]_lut_out, GLOBAL(clock), !GLOBAL(sclrp), , , , );

--N81_cout[2] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|cout[2] at LC6_C20
--operation mode is arithmetic

N81_cout[2] = CARRY(T21L2 & (N81_cout[1] # !T61L4) # !T21L2 & !T61L4 & N81_cout[1]);


--N12_cs_buffer[8] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] at LC2_C10
--operation mode is arithmetic

N12_cs_buffer[8] = N21_sout_node[10] $ N51_sout_node[6] $ N12_cout[7];

--N12_cout[8] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[8] at LC2_C10
--operation mode is arithmetic

N12_cout[8] = CARRY(N21_sout_node[10] & (N51_sout_node[6] # N12_cout[7]) # !N21_sout_node[10] & N51_sout_node[6] & N12_cout[7]);


--N42_cs_buffer[3] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] at LC6_C33
--operation mode is arithmetic

N42_cs_buffer[3] = N12_cs_buffer[7] $ N81_sout_node[1] $ N42_cout[2];

--N42_cout[3] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[3] at LC6_C33
--operation mode is arithmetic

N42_cout[3] = CARRY(N12_cs_buffer[7] & (N81_sout_node[1] # N42_cout[2]) # !N12_cs_buffer[7] & N81_sout_node[1] & N42_cout[2]);


--N9_cs_buffer[8] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] at LC4_C29
--operation mode is arithmetic

N9_cs_buffer[8] = N42_cs_buffer[2] $ N9_cout[7];

--N9_cout[8] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[8] at LC4_C29
--operation mode is arithmetic

N9_cout[8] = CARRY(N42_cs_buffer[2] & N9_cout[7]);


--Q1_q[8] is SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[8] at EC1_E
Q1_q[8]_write_address = WR_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[8]_read_address = RD_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[8] = MEMORY_SEGMENT(, , , , , , , , Q1_q[8]_write_address, Q1_q[8]_read_address);


--H1L81Q is SubDDS:SubDDSi|SAdderSub:u9|result[31]~reg0 at LC4_F14
--operation mode is arithmetic

H1L81Q_lut_out = H1L1;
H1L81Q = DFFEA(H1L81Q_lut_out, GLOBAL(clock), , , , , );

--N3_cout[0] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[0] at LC4_F14
--operation mode is arithmetic

N3_cout[0] = CARRY(!H1L81Q);


--L1_unreg_res_node[31] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|unreg_res_node[31] at LC5_F18
--operation mode is normal

L1_unreg_res_node[31] = N3_cout[30] $ H1L81Q;


--N51_sout_node[10] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|sout_node[10] at LC5_C5
--operation mode is arithmetic

N51_sout_node[10]_lut_out = T4L1 $ T6L1 $ N51_cout[9];
N51_sout_node[10] = DFFEA(N51_sout_node[10]_lut_out, GLOBAL(clock), !GLOBAL(sclrp), , , , );

--N51_cout[10] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cout[10] at LC5_C5
--operation mode is arithmetic

N51_cout[10] = CARRY(T4L1 & (T6L1 # N51_cout[9]) # !T4L1 & T6L1 & N51_cout[9]);


--T2L2 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:$00034|right_bit[0]~0 at LC3_C18
--operation mode is normal

T2L2 = !G1_dataaint[9] & !G1_databint[0] & G1_databint[1];


--T2L1 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:$00034|left_bit[0]~45 at LC8_C14
--operation mode is normal

T2L1 = G1_databint[0] & (G1_dataaint[9] $ G1_databint[1]);


--N21_sout_node[10] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|sout_node[10] at LC5_C14
--operation mode is arithmetic

N21_sout_node[10]_lut_out = N21_cout[9] $ (T2L1 # T2L2);
N21_sout_node[10] = DFFEA(N21_sout_node[10]_lut_out, GLOBAL(clock), !GLOBAL(sclrp), , , , );

--N21_cout[10] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[10] at LC5_C14
--operation mode is arithmetic

N21_cout[10] = CARRY(N21_cout[9] & (T2L1 # T2L2));


--G1_dataaint[7] is SubDDS:SubDDSi|AltiMult:Product1i|dataaint[7] at LC1_C18
--operation mode is normal

G1_dataaint[7]_lut_out = !sclrp & Q1_q[7];
G1_dataaint[7] = DFFEA(G1_dataaint[7]_lut_out, GLOBAL(clock), , , , , );


--T21L7 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_last_mod|left_bit[6]~6 at LC2_C18
--operation mode is normal

T21L7 = G1_databint[7] & G1_dataaint[7];


--H1L9Q is SubDDS:SubDDSi|SAdderSub:u9|result[22]~reg0 at LC1_F17
--operation mode is normal

H1L9Q_lut_out = !sclrp & N72_cs_buffer[7];
H1L9Q = DFFEA(H1L9Q_lut_out, GLOBAL(clock), , , , , );


--H1L01Q is SubDDS:SubDDSi|SAdderSub:u9|result[23]~reg0 at LC2_F12
--operation mode is normal

H1L01Q_lut_out = !sclrp & N72_cs_buffer[8];
H1L01Q = DFFEA(H1L01Q_lut_out, GLOBAL(clock), , , , , );


--H1L11Q is SubDDS:SubDDSi|SAdderSub:u9|result[24]~reg0 at LC8_F17
--operation mode is normal

H1L11Q_lut_out = !sclrp & N72_cs_buffer[9];
H1L11Q = DFFEA(H1L11Q_lut_out, GLOBAL(clock), , , , , );


--H1L21Q is SubDDS:SubDDSi|SAdderSub:u9|result[25]~reg0 at LC1_F7
--operation mode is normal

H1L21Q_lut_out = !sclrp & N72_cs_buffer[10];
H1L21Q = DFFEA(H1L21Q_lut_out, GLOBAL(clock), , , , , );


--H1L31Q is SubDDS:SubDDSi|SAdderSub:u9|result[26]~reg0 at LC2_F8
--operation mode is normal

H1L31Q_lut_out = !sclrp & N72_cs_buffer[11];
H1L31Q = DFFEA(H1L31Q_lut_out, GLOBAL(clock), , , , , );


--H1L41Q is SubDDS:SubDDSi|SAdderSub:u9|result[27]~reg0 at LC6_F18
--operation mode is normal

H1L41Q_lut_out = !sclrp & N72_cs_buffer[12];
H1L41Q = DFFEA(H1L41Q_lut_out, GLOBAL(clock), , , , , );


--H1L51Q is SubDDS:SubDDSi|SAdderSub:u9|result[28]~reg0 at LC6_F15
--operation mode is normal

H1L51Q_lut_out = !sclrp & N72_cs_buffer[13];
H1L51Q = DFFEA(H1L51Q_lut_out, GLOBAL(clock), , , , , );


--H1L61Q is SubDDS:SubDDSi|SAdderSub:u9|result[29]~reg0 at LC7_F15
--operation mode is normal

H1L61Q_lut_out = !sclrp & N72_cs_buffer[14];
H1L61Q = DFFEA(H1L61Q_lut_out, GLOBAL(clock), , , , , );


--H1L71Q is SubDDS:SubDDSi|SAdderSub:u9|result[30]~reg0 at LC7_F18
--operation mode is normal

H1L71Q_lut_out = !sclrp & N72_cs_buffer[15];
H1L71Q = DFFEA(H1L71Q_lut_out, GLOBAL(clock), , , , , );


--G1_dataaint[6] is SubDDS:SubDDSi|AltiMult:Product1i|dataaint[6] at LC6_C17
--operation mode is normal

G1_dataaint[6]_lut_out = !sclrp & Q1_q[6];
G1_dataaint[6] = DFFEA(G1_dataaint[6]_lut_out, GLOBAL(clock), , , , , );


--T21L6 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_last_mod|left_bit[5]~5 at LC2_C16
--operation mode is normal

T21L6 = G1_databint[7] & G1_dataaint[6];


--G1_dataaint[5] is SubDDS:SubDDSi|AltiMult:Product1i|dataaint[5] at LC1_F19
--operation mode is normal

G1_dataaint[5]_lut_out = !sclrp & Q1_q[5];
G1_dataaint[5] = DFFEA(G1_dataaint[5]_lut_out, GLOBAL(clock), , , , , );


--T21L5 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_last_mod|left_bit[4]~4 at LC8_C25
--operation mode is normal

T21L5 = G1_databint[7] & G1_dataaint[5];


--N51_sout_node[9] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|sout_node[9] at LC4_C5
--operation mode is arithmetic

N51_sout_node[9]_lut_out = T4L1 $ T51L9 $ !N51_cout[8];
N51_sout_node[9] = DFFEA(N51_sout_node[9]_lut_out, GLOBAL(clock), !GLOBAL(sclrp), , , , );

--N51_cout[9] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cout[9] at LC4_C5
--operation mode is arithmetic

N51_cout[9] = CARRY(T4L1 & (N51_cout[8] # !T51L9) # !T4L1 & !T51L9 & N51_cout[8]);


--G1_dataaint[4] is SubDDS:SubDDSi|AltiMult:Product1i|dataaint[4] at LC2_C21
--operation mode is normal

G1_dataaint[4]_lut_out = !sclrp & Q1_q[4];
G1_dataaint[4] = DFFEA(G1_dataaint[4]_lut_out, GLOBAL(clock), , , , , );


--T21L4 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_last_mod|left_bit[3]~3 at LC2_C20
--operation mode is normal

T21L4 = G1_databint[7] & G1_dataaint[4];


--N51_sout_node[8] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|sout_node[8] at LC3_C5
--operation mode is arithmetic

N51_sout_node[8]_lut_out = T4L1 $ T51L8 $ !N51_cout[7];
N51_sout_node[8] = DFFEA(N51_sout_node[8]_lut_out, GLOBAL(clock), !GLOBAL(sclrp), , , , );

--N51_cout[8] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cout[8] at LC3_C5
--operation mode is arithmetic

N51_cout[8] = CARRY(T4L1 & (N51_cout[7] # !T51L8) # !T4L1 & !T51L8 & N51_cout[7]);


--G1_dataaint[3] is SubDDS:SubDDSi|AltiMult:Product1i|dataaint[3] at LC1_F22
--operation mode is normal

G1_dataaint[3]_lut_out = !sclrp & Q1_q[3];
G1_dataaint[3] = DFFEA(G1_dataaint[3]_lut_out, GLOBAL(clock), , , , , );


--T21L3 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_last_mod|left_bit[2]~2 at LC8_C24
--operation mode is normal

T21L3 = G1_databint[7] & G1_dataaint[3];


--N51_sout_node[7] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|sout_node[7] at LC2_C5
--operation mode is arithmetic