dds.fit.eqn

DDS的DSP实现

--G1_databint[2] is SubDDS:SubDDSi|AltiMult:Product1i|databint[2] at LC8_C4
--operation mode is normal

G1_databint[2]_lut_out = !sclrp & iAMPlifys[2];
G1_databint[2] = DFFEA(G1_databint[2]_lut_out, GLOBAL(clock), , , , , );


--G1_databint[1] is SubDDS:SubDDSi|AltiMult:Product1i|databint[1] at LC6_C18
--operation mode is normal

G1_databint[1]_lut_out = !sclrp & iAMPlifys[1];
G1_databint[1] = DFFEA(G1_databint[1]_lut_out, GLOBAL(clock), , , , , );


--G1_databint[3] is SubDDS:SubDDSi|AltiMult:Product1i|databint[3] at LC2_C9
--operation mode is normal

G1_databint[3]_lut_out = !sclrp & iAMPlifys[3];
G1_databint[3] = DFFEA(G1_databint[3]_lut_out, GLOBAL(clock), , , , , );


--T4L1 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:$00038|out_bit[0]~0 at LC5_C4
--operation mode is normal

T4L1 = G1_databint[3] & !G1_dataaint[9] & (!G1_databint[2] # !G1_databint[1]) # !G1_databint[3] & G1_dataaint[9] & (G1_databint[1] # G1_databint[2]);


--G1_databint[4] is SubDDS:SubDDSi|AltiMult:Product1i|databint[4] at LC5_C9
--operation mode is normal

G1_databint[4]_lut_out = !sclrp & iAMPlifys[4];
G1_databint[4] = DFFEA(G1_databint[4]_lut_out, GLOBAL(clock), , , , , );


--T6L1 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:$00042|out_bit[0]~0 at LC6_C16
--operation mode is normal

T6L1 = G1_databint[5] & !G1_dataaint[9] & (!G1_databint[4] # !G1_databint[3]) # !G1_databint[5] & G1_dataaint[9] & (G1_databint[3] # G1_databint[4]);


--N21_sout_node[12] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|sout_node[12] at LC7_C14
--operation mode is normal

N21_sout_node[12]_lut_out = N21_cout[11] $ (G1_dataaint[9] & G1_databint[0] & !G1_databint[1] # !G1_dataaint[9] & G1_databint[1]);
N21_sout_node[12] = DFFEA(N21_sout_node[12]_lut_out, GLOBAL(clock), !GLOBAL(sclrp), , , , );


--N21_sout_node[11] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|sout_node[11] at LC6_C14
--operation mode is arithmetic

N21_sout_node[11]_lut_out = N21_cout[10] $ (T2L1 # T2L2);
N21_sout_node[11] = DFFEA(N21_sout_node[11]_lut_out, GLOBAL(clock), !GLOBAL(sclrp), , , , );

--N21_cout[11] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[11] at LC6_C14
--operation mode is arithmetic

N21_cout[11] = CARRY(N21_cout[10] & (T2L1 # T2L2));


--G1_databint[0] is SubDDS:SubDDSi|AltiMult:Product1i|databint[0] at LC7_C18
--operation mode is normal

G1_databint[0]_lut_out = !sclrp & iAMPlifys[0];
G1_databint[0] = DFFEA(G1_databint[0]_lut_out, GLOBAL(clock), , , , , );


--G1_dataaint[8] is SubDDS:SubDDSi|AltiMult:Product1i|dataaint[8] at LC5_C17
--operation mode is normal

G1_dataaint[8]_lut_out = !sclrp & Q1_q[8];
G1_dataaint[8] = DFFEA(G1_dataaint[8]_lut_out, GLOBAL(clock), , , , , );


--T21L8 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_last_mod|left_bit[7]~7 at LC5_C6
--operation mode is normal

T21L8 = G1_databint[7] & G1_dataaint[8];


--N81_sout_node[7] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|sout_node[7] at LC3_C22
--operation mode is arithmetic

N81_sout_node[7]_lut_out = T61L9 $ T21L7 $ !N81_cout[6];
N81_sout_node[7] = DFFEA(N81_sout_node[7]_lut_out, GLOBAL(clock), !GLOBAL(sclrp), , , , );

--N81_cout[7] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|cout[7] at LC3_C22
--operation mode is arithmetic

N81_cout[7] = CARRY(T61L9 & T21L7 & N81_cout[6] # !T61L9 & (T21L7 # N81_cout[6]));


--N3_cs_buffer[22] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[22] at LC4_F16
--operation mode is arithmetic

N3_cs_buffer[22] = H1L9Q $ N3_cout[21];

--N3_cout[22] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[22] at LC4_F16
--operation mode is arithmetic

N3_cout[22] = CARRY(H1L9Q & N3_cout[21]);


--N3_cs_buffer[23] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[23] at LC5_F16
--operation mode is arithmetic

N3_cs_buffer[23] = H1L01Q $ N3_cout[22];

--N3_cout[23] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[23] at LC5_F16
--operation mode is arithmetic

N3_cout[23] = CARRY(H1L01Q & N3_cout[22]);


--N3_cs_buffer[24] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[24] at LC6_F16
--operation mode is arithmetic

N3_cs_buffer[24] = H1L11Q $ N3_cout[23];

--N3_cout[24] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[24] at LC6_F16
--operation mode is arithmetic

N3_cout[24] = CARRY(H1L11Q & N3_cout[23]);


--N3_cs_buffer[25] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[25] at LC7_F16
--operation mode is arithmetic

N3_cs_buffer[25] = H1L21Q $ N3_cout[24];

--N3_cout[25] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[25] at LC7_F16
--operation mode is arithmetic

N3_cout[25] = CARRY(H1L21Q & N3_cout[24]);


--N3_cs_buffer[26] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[26] at LC8_F16
--operation mode is arithmetic

N3_cs_buffer[26] = H1L31Q $ N3_cout[25];

--N3_cout[26] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[26] at LC8_F16
--operation mode is arithmetic

N3_cout[26] = CARRY(H1L31Q & N3_cout[25]);


--N3_cs_buffer[27] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[27] at LC1_F18
--operation mode is arithmetic

N3_cs_buffer[27] = H1L41Q $ N3_cout[26];

--N3_cout[27] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[27] at LC1_F18
--operation mode is arithmetic

N3_cout[27] = CARRY(H1L41Q & N3_cout[26]);


--N3_cs_buffer[28] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[28] at LC2_F18
--operation mode is arithmetic

N3_cs_buffer[28] = H1L51Q $ N3_cout[27];

--N3_cout[28] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[28] at LC2_F18
--operation mode is arithmetic

N3_cout[28] = CARRY(H1L51Q & N3_cout[27]);


--N3_cs_buffer[29] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[29] at LC3_F18
--operation mode is arithmetic

N3_cs_buffer[29] = H1L61Q $ N3_cout[28];

--N3_cout[29] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[29] at LC3_F18
--operation mode is arithmetic

N3_cout[29] = CARRY(H1L61Q & N3_cout[28]);


--N3_cs_buffer[30] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[30] at LC4_F18
--operation mode is arithmetic

N3_cs_buffer[30] = H1L71Q $ N3_cout[29];

--N3_cout[30] is SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[30] at LC4_F18
--operation mode is arithmetic

N3_cout[30] = CARRY(H1L71Q & N3_cout[29]);


--N12_cs_buffer[12] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[12] at LC6_C10
--operation mode is arithmetic

N12_cs_buffer[12] = N21_sout_node[12] $ N51_sout_node[10] $ N12_cout[11];

--N12_cout[12] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[12] at LC6_C10
--operation mode is arithmetic

N12_cout[12] = CARRY(N21_sout_node[12] & (N51_sout_node[10] # N12_cout[11]) # !N21_sout_node[12] & N51_sout_node[10] & N12_cout[11]);


--N81_sout_node[6] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|sout_node[6] at LC2_C22
--operation mode is arithmetic

N81_sout_node[6]_lut_out = T21L6 $ T61L8 $ !N81_cout[5];
N81_sout_node[6] = DFFEA(N81_sout_node[6]_lut_out, GLOBAL(clock), !GLOBAL(sclrp), , , , );

--N81_cout[6] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|cout[6] at LC2_C22
--operation mode is arithmetic

N81_cout[6] = CARRY(T21L6 & (N81_cout[5] # !T61L8) # !T21L6 & !T61L8 & N81_cout[5]);


--N81_sout_node[5] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|sout_node[5] at LC1_C22
--operation mode is arithmetic

N81_sout_node[5]_lut_out = T21L5 $ T61L7 $ !N81_cout[4];
N81_sout_node[5] = DFFEA(N81_sout_node[5]_lut_out, GLOBAL(clock), !GLOBAL(sclrp), , , , );

--N81_cout[5] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|cout[5] at LC1_C22
--operation mode is arithmetic

N81_cout[5] = CARRY(T21L5 & (N81_cout[4] # !T61L7) # !T21L5 & !T61L7 & N81_cout[4]);


--N12_cs_buffer[11] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[11] at LC5_C10
--operation mode is arithmetic

N12_cs_buffer[11] = N21_sout_node[12] $ N51_sout_node[9] $ N12_cout[10];

--N12_cout[11] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[11] at LC5_C10
--operation mode is arithmetic

N12_cout[11] = CARRY(N21_sout_node[12] & (N51_sout_node[9] # N12_cout[10]) # !N21_sout_node[12] & N51_sout_node[9] & N12_cout[10]);


--N81_sout_node[4] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|sout_node[4] at LC8_C20
--operation mode is arithmetic

N81_sout_node[4]_lut_out = T21L4 $ T61L6 $ !N81_cout[3];
N81_sout_node[4] = DFFEA(N81_sout_node[4]_lut_out, GLOBAL(clock), !GLOBAL(sclrp), , , , );

--N81_cout[4] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|cout[4] at LC8_C20
--operation mode is arithmetic

N81_cout[4] = CARRY(T21L4 & (N81_cout[3] # !T61L6) # !T21L4 & !T61L6 & N81_cout[3]);


--N12_cs_buffer[10] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] at LC4_C10
--operation mode is arithmetic

N12_cs_buffer[10] = N21_sout_node[12] $ N51_sout_node[8] $ N12_cout[9];

--N12_cout[10] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[10] at LC4_C10
--operation mode is arithmetic

N12_cout[10] = CARRY(N21_sout_node[12] & (N51_sout_node[8] # N12_cout[9]) # !N21_sout_node[12] & N51_sout_node[8] & N12_cout[9]);


--N81_sout_node[3] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|sout_node[3] at LC7_C20
--operation mode is arithmetic

N81_sout_node[3]_lut_out = T21L3 $ T61L5 $ !N81_cout[2];
N81_sout_node[3] = DFFEA(N81_sout_node[3]_lut_out, GLOBAL(clock), !GLOBAL(sclrp), , , , );

--N81_cout[3] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|cout[3] at LC7_C20
--operation mode is arithmetic

N81_cout[3] = CARRY(T21L3 & (N81_cout[2] # !T61L5) # !T21L3 & !T61L5 & N81_cout[2]);