dds.fit.eqn

DDS的DSP实现

--operation mode is arithmetic

N9_cs_buffer[16] = N42_cs_buffer[10] $ N9_cout[15];

--N9_cout[16] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[16] at LC4_C31
--operation mode is arithmetic

N9_cout[16] = CARRY(N42_cs_buffer[10] & N9_cout[15]);


--L3_unreg_res_node[17] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|unreg_res_node[17] at LC5_C31
--operation mode is normal

L3_unreg_res_node[17] = N9_cout[16] $ L8_unreg_res_node[11];


--N9_cs_buffer[15] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[15] at LC3_C31
--operation mode is arithmetic

N9_cs_buffer[15] = N42_cs_buffer[9] $ N9_cout[14];

--N9_cout[15] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[15] at LC3_C31
--operation mode is arithmetic

N9_cout[15] = CARRY(N42_cs_buffer[9] & N9_cout[14]);


--N9_cs_buffer[14] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[14] at LC2_C31
--operation mode is arithmetic

N9_cs_buffer[14] = N42_cs_buffer[8] $ N9_cout[13];

--N9_cout[14] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[14] at LC2_C31
--operation mode is arithmetic

N9_cout[14] = CARRY(N42_cs_buffer[8] & N9_cout[13]);


--N9_cs_buffer[13] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[13] at LC1_C31
--operation mode is arithmetic

N9_cs_buffer[13] = N42_cs_buffer[7] $ N9_cout[12];

--N9_cout[13] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[13] at LC1_C31
--operation mode is arithmetic

N9_cout[13] = CARRY(N42_cs_buffer[7] & N9_cout[12]);


--N9_cs_buffer[12] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[12] at LC8_C29
--operation mode is arithmetic

N9_cs_buffer[12] = N42_cs_buffer[6] $ N9_cout[11];

--N9_cout[12] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[12] at LC8_C29
--operation mode is arithmetic

N9_cout[12] = CARRY(N42_cs_buffer[6] & N9_cout[11]);


--N9_cs_buffer[11] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[11] at LC7_C29
--operation mode is arithmetic

N9_cs_buffer[11] = N42_cs_buffer[5] $ N9_cout[10];

--N9_cout[11] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[11] at LC7_C29
--operation mode is arithmetic

N9_cout[11] = CARRY(N42_cs_buffer[5] & N9_cout[10]);


--N9_cs_buffer[10] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] at LC6_C29
--operation mode is arithmetic

N9_cs_buffer[10] = N42_cs_buffer[4] $ N9_cout[9];

--N9_cout[10] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[10] at LC6_C29
--operation mode is arithmetic

N9_cout[10] = CARRY(N42_cs_buffer[4] & N9_cout[9]);


--N42_cs_buffer[10] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] at LC5_C35
--operation mode is arithmetic

N42_cs_buffer[10] = L7_unreg_res_node[14] $ N81_sout_node[8] $ N42_cout[9];

--N42_cout[10] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[10] at LC5_C35
--operation mode is arithmetic

N42_cout[10] = CARRY(L7_unreg_res_node[14] & (N81_sout_node[8] # N42_cout[9]) # !L7_unreg_res_node[14] & N81_sout_node[8] & N42_cout[9]);


--L8_unreg_res_node[11] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|unreg_res_node[11] at LC6_C35
--operation mode is normal

L8_unreg_res_node[11] = N81_sout_node[9] $ N42_cout[10] $ L7_unreg_res_node[14];


--N81_sout_node[9] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|sout_node[9] at LC5_C22
--operation mode is normal

N81_sout_node[9]_lut_out = T8L1 $ N81_cout[8] $ (G1_databint[7] & G1_dataaint[9]);
N81_sout_node[9] = DFFEA(N81_sout_node[9]_lut_out, GLOBAL(clock), !GLOBAL(sclrp), , , , );


--N81_sout_node[8] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|sout_node[8] at LC4_C22
--operation mode is arithmetic

N81_sout_node[8]_lut_out = T8L1 $ T21L8 $ N81_cout[7];
N81_sout_node[8] = DFFEA(N81_sout_node[8]_lut_out, GLOBAL(clock), !GLOBAL(sclrp), , , , );

--N81_cout[8] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[2]|addcore:adder|a_csnbuffer:result_node|cout[8] at LC4_C22
--operation mode is arithmetic

N81_cout[8] = CARRY(T8L1 & (T21L8 # N81_cout[7]) # !T8L1 & T21L8 & N81_cout[7]);


--G1_databint[5] is SubDDS:SubDDSi|AltiMult:Product1i|databint[5] at LC1_C9
--operation mode is normal

G1_databint[5]_lut_out = !sclrp & iAMPlifys[5];
G1_databint[5] = DFFEA(G1_databint[5]_lut_out, GLOBAL(clock), , , , , );


--G1_databint[6] is SubDDS:SubDDSi|AltiMult:Product1i|databint[6] at LC7_C25
--operation mode is normal

G1_databint[6]_lut_out = !sclrp & iAMPlifys[6];
G1_databint[6] = DFFEA(G1_databint[6]_lut_out, GLOBAL(clock), , , , , );


--G1_dataaint[9] is SubDDS:SubDDSi|AltiMult:Product1i|dataaint[9] at LC2_C19
--operation mode is normal

G1_dataaint[9]_lut_out = !sclrp & Q1_q[9];
G1_dataaint[9] = DFFEA(G1_dataaint[9]_lut_out, GLOBAL(clock), , , , , );


--G1_databint[7] is SubDDS:SubDDSi|AltiMult:Product1i|databint[7] at LC3_C21
--operation mode is normal

G1_databint[7]_lut_out = !sclrp & iAMPlifys[7];
G1_databint[7] = DFFEA(G1_databint[7]_lut_out, GLOBAL(clock), , , , , );


--T8L1 is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:$00046|out_bit[0]~0 at LC6_C22
--operation mode is normal

T8L1 = G1_databint[7] & !G1_dataaint[9] & (!G1_databint[5] # !G1_databint[6]) # !G1_databint[7] & G1_dataaint[9] & (G1_databint[6] # G1_databint[5]);


--N12_cs_buffer[13] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[13] at LC7_C10
--operation mode is arithmetic

N12_cs_buffer[13] = N21_sout_node[12] $ N51_sout_node[11] $ N12_cout[12];

--N12_cout[13] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[13] at LC7_C10
--operation mode is arithmetic

N12_cout[13] = CARRY(N21_sout_node[12] & (N51_sout_node[11] # N12_cout[12]) # !N21_sout_node[12] & N51_sout_node[11] & N12_cout[12]);


--L7_unreg_res_node[14] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|unreg_res_node[14] at LC8_C10
--operation mode is normal

L7_unreg_res_node[14] = N51_sout_node[12] $ N12_cout[13] $ N21_sout_node[12];


--N42_cs_buffer[9] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[9] at LC4_C35
--operation mode is arithmetic

N42_cs_buffer[9] = N12_cs_buffer[13] $ N81_sout_node[7] $ N42_cout[8];

--N42_cout[9] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[9] at LC4_C35
--operation mode is arithmetic

N42_cout[9] = CARRY(N12_cs_buffer[13] & (N81_sout_node[7] # N42_cout[8]) # !N12_cs_buffer[13] & N81_sout_node[7] & N42_cout[8]);


--N42_cs_buffer[8] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] at LC3_C35
--operation mode is arithmetic

N42_cs_buffer[8] = N12_cs_buffer[12] $ N81_sout_node[6] $ N42_cout[7];

--N42_cout[8] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[8] at LC3_C35
--operation mode is arithmetic

N42_cout[8] = CARRY(N12_cs_buffer[12] & (N81_sout_node[6] # N42_cout[7]) # !N12_cs_buffer[12] & N81_sout_node[6] & N42_cout[7]);


--N42_cs_buffer[7] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] at LC2_C35
--operation mode is arithmetic

N42_cs_buffer[7] = N12_cs_buffer[11] $ N81_sout_node[5] $ N42_cout[6];

--N42_cout[7] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[7] at LC2_C35
--operation mode is arithmetic

N42_cout[7] = CARRY(N12_cs_buffer[11] & (N81_sout_node[5] # N42_cout[6]) # !N12_cs_buffer[11] & N81_sout_node[5] & N42_cout[6]);


--N42_cs_buffer[6] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] at LC1_C35
--operation mode is arithmetic

N42_cs_buffer[6] = N12_cs_buffer[10] $ N81_sout_node[4] $ N42_cout[5];

--N42_cout[6] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[6] at LC1_C35
--operation mode is arithmetic

N42_cout[6] = CARRY(N12_cs_buffer[10] & (N81_sout_node[4] # N42_cout[5]) # !N12_cs_buffer[10] & N81_sout_node[4] & N42_cout[5]);


--N42_cs_buffer[5] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] at LC8_C33
--operation mode is arithmetic

N42_cs_buffer[5] = N12_cs_buffer[9] $ N81_sout_node[3] $ N42_cout[4];

--N42_cout[5] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[5] at LC8_C33
--operation mode is arithmetic

N42_cout[5] = CARRY(N12_cs_buffer[9] & (N81_sout_node[3] # N42_cout[4]) # !N12_cs_buffer[9] & N81_sout_node[3] & N42_cout[4]);


--N42_cs_buffer[4] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] at LC7_C33
--operation mode is arithmetic

N42_cs_buffer[4] = N12_cs_buffer[8] $ N81_sout_node[2] $ N42_cout[3];

--N42_cout[4] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|mpar_add:sub_par_add|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cout[4] at LC7_C33
--operation mode is arithmetic

N42_cout[4] = CARRY(N12_cs_buffer[8] & (N81_sout_node[2] # N42_cout[3]) # !N12_cs_buffer[8] & N81_sout_node[2] & N42_cout[3]);


--N9_cs_buffer[9] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[9] at LC5_C29
--operation mode is arithmetic

N9_cs_buffer[9] = N42_cs_buffer[3] $ N9_cout[8];

--N9_cout[9] is SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[9] at LC5_C29
--operation mode is arithmetic

N9_cout[9] = CARRY(N42_cs_buffer[3] & N9_cout[8]);


--Q1_q[9] is SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[9] at EC1_C
Q1_q[9]_write_address = WR_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[9]_read_address = RD_ADDR(N3_cs_buffer[22], N3_cs_buffer[23], N3_cs_buffer[24], N3_cs_buffer[25], N3_cs_buffer[26], N3_cs_buffer[27], N3_cs_buffer[28], N3_cs_buffer[29], N3_cs_buffer[30], L1_unreg_res_node[31]);
Q1_q[9] = MEMORY_SEGMENT(, , , , , , , , Q1_q[9]_write_address, Q1_q[9]_read_address);


--N51_sout_node[12] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|sout_node[12] at LC7_C5
--operation mode is normal

N51_sout_node[12]_lut_out = T4L1 $ N51_cout[11] $ T6L1;
N51_sout_node[12] = DFFEA(N51_sout_node[12]_lut_out, GLOBAL(clock), !GLOBAL(sclrp), , , , );


--N51_sout_node[11] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|sout_node[11] at LC6_C5
--operation mode is arithmetic

N51_sout_node[11]_lut_out = T4L1 $ T6L1 $ N51_cout[10];
N51_sout_node[11] = DFFEA(N51_sout_node[11]_lut_out, GLOBAL(clock), !GLOBAL(sclrp), , , , );

--N51_cout[11] is SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|addcore:adder|a_csnbuffer:result_node|cout[11] at LC6_C5
--operation mode is arithmetic

N51_cout[11] = CARRY(T4L1 & (T6L1 # N51_cout[10]) # !T4L1 & T6L1 & N51_cout[10]);