dds.map.qmsg

来自「DDS的DSP实现」· QMSG 代码 · 共 180 行 · 第 1/4 页

QMSG
180 行
字号
1234
{ "Info" "IVRFX_VHDL_ANOTHER_MATCH" "lpm_pack.vhd(201) " "Info: VHDL information at lpm_pack.vhd(201): duplicate match" {  } { { "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" "" "" { Text "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" 201 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_USE_CLAUSES_IMPORTING_MULTIPLE_DECLS" "std_logic_2d DSPBUILDER.VHD(4764) " "Warning: VHDL Use Clause warning at DSPBUILDER.VHD(4764): more than one Use Clause imports a declaration of simple name std_logic_2d -- none of the declarations are directly visible" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDER.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDER.VHD" 4764 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_IS_DECLARED_HERE" "std_logic_2d DSPBUILDERPACK.VHD(33) " "Info: VHDL information: object std_logic_2d is declared at DSPBUILDERPACK.VHD(33)" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" 33 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_ANOTHER_MATCH" "lpm_pack.vhd(201) " "Info: VHDL information at lpm_pack.vhd(201): duplicate match" {  } { { "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" "" "" { Text "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" 201 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_USE_CLAUSES_IMPORTING_MULTIPLE_DECLS" "std_logic_2d  DSPBUILDER.VHD(4764) " "Warning: VHDL Use Clause warning at DSPBUILDER.VHD(4764): more than one Use Clause imports a declaration of simple name std_logic_2d  -- none of the declarations are directly visible" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDER.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDER.VHD" 4764 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_IS_DECLARED_HERE" "std_logic_2d  DSPBUILDERPACK.VHD(33) " "Info: VHDL information: object std_logic_2d  is declared at DSPBUILDERPACK.VHD(33)" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" 33 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_ANOTHER_MATCH" "lpm_pack.vhd(201) " "Info: VHDL information at lpm_pack.vhd(201): duplicate match" {  } { { "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" "" "" { Text "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" 201 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_USE_CLAUSES_IMPORTING_MULTIPLE_DECLS" "std_logic_2d DSPBUILDER.VHD(5016) " "Warning: VHDL Use Clause warning at DSPBUILDER.VHD(5016): more than one Use Clause imports a declaration of simple name std_logic_2d -- none of the declarations are directly visible" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDER.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDER.VHD" 5016 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_IS_DECLARED_HERE" "std_logic_2d DSPBUILDERPACK.VHD(33) " "Info: VHDL information: object std_logic_2d is declared at DSPBUILDERPACK.VHD(33)" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" 33 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_ANOTHER_MATCH" "lpm_pack.vhd(201) " "Info: VHDL information at lpm_pack.vhd(201): duplicate match" {  } { { "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" "" "" { Text "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" 201 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_USE_CLAUSES_IMPORTING_MULTIPLE_DECLS" "std_logic_2d  DSPBUILDER.VHD(5016) " "Warning: VHDL Use Clause warning at DSPBUILDER.VHD(5016): more than one Use Clause imports a declaration of simple name std_logic_2d  -- none of the declarations are directly visible" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDER.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDER.VHD" 5016 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_IS_DECLARED_HERE" "std_logic_2d  DSPBUILDERPACK.VHD(33) " "Info: VHDL information: object std_logic_2d  is declared at DSPBUILDERPACK.VHD(33)" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" 33 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_ANOTHER_MATCH" "lpm_pack.vhd(201) " "Info: VHDL information at lpm_pack.vhd(201): duplicate match" {  } { { "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" "" "" { Text "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" 201 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_USE_CLAUSES_IMPORTING_MULTIPLE_DECLS" "std_logic_2d DSPBUILDER.VHD(5222) " "Warning: VHDL Use Clause warning at DSPBUILDER.VHD(5222): more than one Use Clause imports a declaration of simple name std_logic_2d -- none of the declarations are directly visible" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDER.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDER.VHD" 5222 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_IS_DECLARED_HERE" "std_logic_2d DSPBUILDERPACK.VHD(33) " "Info: VHDL information: object std_logic_2d is declared at DSPBUILDERPACK.VHD(33)" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" 33 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_ANOTHER_MATCH" "lpm_pack.vhd(201) " "Info: VHDL information at lpm_pack.vhd(201): duplicate match" {  } { { "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" "" "" { Text "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" 201 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_USE_CLAUSES_IMPORTING_MULTIPLE_DECLS" "std_logic_2d  DSPBUILDER.VHD(5222) " "Warning: VHDL Use Clause warning at DSPBUILDER.VHD(5222): more than one Use Clause imports a declaration of simple name std_logic_2d  -- none of the declarations are directly visible" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDER.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDER.VHD" 5222 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_IS_DECLARED_HERE" "std_logic_2d  DSPBUILDERPACK.VHD(33) " "Info: VHDL information: object std_logic_2d  is declared at DSPBUILDERPACK.VHD(33)" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" 33 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_ANOTHER_MATCH" "lpm_pack.vhd(201) " "Info: VHDL information at lpm_pack.vhd(201): duplicate match" {  } { { "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" "" "" { Text "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" 201 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_USE_CLAUSES_IMPORTING_MULTIPLE_DECLS" "std_logic_2d DSPBUILDER.VHD(5410) " "Warning: VHDL Use Clause warning at DSPBUILDER.VHD(5410): more than one Use Clause imports a declaration of simple name std_logic_2d -- none of the declarations are directly visible" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDER.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDER.VHD" 5410 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_IS_DECLARED_HERE" "std_logic_2d DSPBUILDERPACK.VHD(33) " "Info: VHDL information: object std_logic_2d is declared at DSPBUILDERPACK.VHD(33)" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" 33 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_ANOTHER_MATCH" "lpm_pack.vhd(201) " "Info: VHDL information at lpm_pack.vhd(201): duplicate match" {  } { { "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" "" "" { Text "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" 201 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_USE_CLAUSES_IMPORTING_MULTIPLE_DECLS" "std_logic_2d  DSPBUILDER.VHD(5410) " "Warning: VHDL Use Clause warning at DSPBUILDER.VHD(5410): more than one Use Clause imports a declaration of simple name std_logic_2d  -- none of the declarations are directly visible" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDER.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDER.VHD" 5410 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_IS_DECLARED_HERE" "std_logic_2d  DSPBUILDERPACK.VHD(33) " "Info: VHDL information: object std_logic_2d  is declared at DSPBUILDERPACK.VHD(33)" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" 33 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_ANOTHER_MATCH" "lpm_pack.vhd(201) " "Info: VHDL information at lpm_pack.vhd(201): duplicate match" {  } { { "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" "" "" { Text "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" 201 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_USE_CLAUSES_IMPORTING_MULTIPLE_DECLS" "std_logic_2d DSPBUILDER.VHD(5611) " "Warning: VHDL Use Clause warning at DSPBUILDER.VHD(5611): more than one Use Clause imports a declaration of simple name std_logic_2d -- none of the declarations are directly visible" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDER.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDER.VHD" 5611 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_IS_DECLARED_HERE" "std_logic_2d DSPBUILDERPACK.VHD(33) " "Info: VHDL information: object std_logic_2d is declared at DSPBUILDERPACK.VHD(33)" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" 33 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_ANOTHER_MATCH" "lpm_pack.vhd(201) " "Info: VHDL information at lpm_pack.vhd(201): duplicate match" {  } { { "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" "" "" { Text "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" 201 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_USE_CLAUSES_IMPORTING_MULTIPLE_DECLS" "std_logic_2d  DSPBUILDER.VHD(5611) " "Warning: VHDL Use Clause warning at DSPBUILDER.VHD(5611): more than one Use Clause imports a declaration of simple name std_logic_2d  -- none of the declarations are directly visible" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDER.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDER.VHD" 5611 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_IS_DECLARED_HERE" "std_logic_2d  DSPBUILDERPACK.VHD(33) " "Info: VHDL information: object std_logic_2d  is declared at DSPBUILDERPACK.VHD(33)" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" 33 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_ANOTHER_MATCH" "lpm_pack.vhd(201) " "Info: VHDL information at lpm_pack.vhd(201): duplicate match" {  } { { "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" "" "" { Text "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" 201 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_USE_CLAUSES_IMPORTING_MULTIPLE_DECLS" "std_logic_2d SubDDS.vhd(28) " "Warning: VHDL Use Clause warning at SubDDS.vhd(28): more than one Use Clause imports a declaration of simple name std_logic_2d -- none of the declarations are directly visible" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/SubDDS.vhd" "" "" { Text "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/SubDDS.vhd" 28 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_IS_DECLARED_HERE" "std_logic_2d lpm_pack.vhd(201) " "Info: VHDL information: object std_logic_2d is declared at lpm_pack.vhd(201)" {  } { { "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" "" "" { Text "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" 201 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_ANOTHER_MATCH" "DSPBUILDERPACK.VHD(33) " "Info: VHDL information at DSPBUILDERPACK.VHD(33): duplicate match" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" 33 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_USE_CLAUSES_IMPORTING_MULTIPLE_DECLS" "std_logic_2d  SubDDS.vhd(28) " "Warning: VHDL Use Clause warning at SubDDS.vhd(28): more than one Use Clause imports a declaration of simple name std_logic_2d  -- none of the declarations are directly visible" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/SubDDS.vhd" "" "" { Text "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/SubDDS.vhd" 28 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_IS_DECLARED_HERE" "std_logic_2d  lpm_pack.vhd(201) " "Info: VHDL information: object std_logic_2d  is declared at lpm_pack.vhd(201)" {  } { { "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" "" "" { Text "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" 201 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_ANOTHER_MATCH" "DSPBUILDERPACK.VHD(33) " "Info: VHDL information at DSPBUILDERPACK.VHD(33): duplicate match" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" 33 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_USE_CLAUSES_IMPORTING_MULTIPLE_DECLS" "std_logic_2d dds.vhd(28) " "Warning: VHDL Use Clause warning at dds.vhd(28): more than one Use Clause imports a declaration of simple name std_logic_2d -- none of the declarations are directly visible" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/dds.vhd" "" "" { Text "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/dds.vhd" 28 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_IS_DECLARED_HERE" "std_logic_2d lpm_pack.vhd(201) " "Info: VHDL information: object std_logic_2d is declared at lpm_pack.vhd(201)" {  } { { "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" "" "" { Text "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" 201 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_ANOTHER_MATCH" "DSPBUILDERPACK.VHD(33) " "Info: VHDL information at DSPBUILDERPACK.VHD(33): duplicate match" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" 33 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_USE_CLAUSES_IMPORTING_MULTIPLE_DECLS" "std_logic_2d  dds.vhd(28) " "Warning: VHDL Use Clause warning at dds.vhd(28): more than one Use Clause imports a declaration of simple name std_logic_2d  -- none of the declarations are directly visible" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/dds.vhd" "" "" { Text "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/dds.vhd" 28 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_IS_DECLARED_HERE" "std_logic_2d  lpm_pack.vhd(201) " "Info: VHDL information: object std_logic_2d  is declared at lpm_pack.vhd(201)" {  } { { "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" "" "" { Text "e:/eda/libraries/vhdl93/lpm/lpm_pack.vhd" 201 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_ANOTHER_MATCH" "DSPBUILDERPACK.VHD(33) " "Info: VHDL information at DSPBUILDERPACK.VHD(33): duplicate match" {  } { { "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" "" "" { Text "D:/MATLAB6/DSPBuilder/Altlib/DSPBUILDERPACK.VHD" 33 0 0 } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 59 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 59 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 11 17:18:12 2004 " "Info: Processing ended: Wed Aug 11 17:18:12 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0}  } {  } 0}
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dds.map.qmsg - 源码说明

本页面展示了「DDS的DSP实现」中的 dds.map.qmsg 源码文件，采用 QMSG 编程语言编写，共 180 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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