dds.tan.qmsg

DDS的DSP实现

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register SubDDS:SubDDSi\|SAdderSub:u9\|result\[17\]~reg0 register SubDDS:SubDDSi\|AltiMult:Product1i\|dataaint\[7\] 46.95 MHz 21.3 ns Internal " "Info: Clock clock has Internal fmax of 46.95 MHz between source register SubDDS:SubDDSi\|SAdderSub:u9\|result\[17\]~reg0 and destination register SubDDS:SubDDSi\|AltiMult:Product1i\|dataaint\[7\] (period= 21.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "20.200 ns + Longest register register " "Info: + Longest register to register delay is 20.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SubDDS:SubDDSi\|SAdderSub:u9\|result\[17\]~reg0 1 REG LC1_F11 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F11; Fanout = 3; REG Node = 'SubDDS:SubDDSi\|SAdderSub:u9\|result\[17\]~reg0'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "" { SubDDS:SubDDSi|SAdderSub:u9|result[17]~reg0 } "NODE_NAME" } } } { "d:/matlab6/DSPBuilder/Altlib/DSPBUILDER.VHD" "" "" { Text "d:/matlab6/DSPBuilder/Altlib/DSPBUILDER.VHD" 1481 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(0.700 ns) 1.900 ns SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[17\] 2 COMB LC7_F14 1 " "Info: 2: + IC(1.200 ns) + CELL(0.700 ns) = 1.900 ns; Loc. = LC7_F14; Fanout = 1; COMB Node = 'SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[17\]'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "1.900 ns" { SubDDS:SubDDSi|SAdderSub:u9|result[17]~reg0 SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[17] } "NODE_NAME" } } } { "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 2.100 ns SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[18\] 3 COMB LC8_F14 1 " "Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 2.100 ns; Loc. = LC8_F14; Fanout = 1; COMB Node = 'SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[18\]'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "0.200 ns" { SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[17] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[18] } "NODE_NAME" } } } { "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.200 ns) 2.800 ns SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[19\] 4 COMB LC1_F16 1 " "Info: 4: + IC(0.500 ns) + CELL(0.200 ns) = 2.800 ns; Loc. = LC1_F16; Fanout = 1; COMB Node = 'SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[19\]'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "0.700 ns" { SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[18] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[19] } "NODE_NAME" } } } { "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 3.000 ns SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[20\] 5 COMB LC2_F16 1 " "Info: 5: + IC(0.000 ns) + CELL(0.200 ns) = 3.000 ns; Loc. = LC2_F16; Fanout = 1; COMB Node = 'SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[20\]'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "0.200 ns" { SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[19] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[20] } "NODE_NAME" } } } { "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 3.200 ns SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[21\] 6 COMB LC3_F16 2 " "Info: 6: + IC(0.000 ns) + CELL(0.200 ns) = 3.200 ns; Loc. = LC3_F16; Fanout = 2; COMB Node = 'SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[21\]'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "0.200 ns" { SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[20] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[21] } "NODE_NAME" } } } { "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 3.400 ns SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[22\] 7 COMB LC4_F16 2 " "Info: 7: + IC(0.000 ns) + CELL(0.200 ns) = 3.400 ns; Loc. = LC4_F16; Fanout = 2; COMB Node = 'SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[22\]'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "0.200 ns" { SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[21] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[22] } "NODE_NAME" } } } { "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 3.600 ns SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[23\] 8 COMB LC5_F16 2 " "Info: 8: + IC(0.000 ns) + CELL(0.200 ns) = 3.600 ns; Loc. = LC5_F16; Fanout = 2; COMB Node = 'SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[23\]'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "0.200 ns" { SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[22] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[23] } "NODE_NAME" } } } { "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 3.800 ns SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[24\] 9 COMB LC6_F16 2 " "Info: 9: + IC(0.000 ns) + CELL(0.200 ns) = 3.800 ns; Loc. = LC6_F16; Fanout = 2; COMB Node = 'SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[24\]'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "0.200 ns" { SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[23] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[24] } "NODE_NAME" } } } { "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.000 ns SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[25\] 10 COMB LC7_F16 2 " "Info: 10: + IC(0.000 ns) + CELL(0.200 ns) = 4.000 ns; Loc. = LC7_F16; Fanout = 2; COMB Node = 'SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[25\]'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "0.200 ns" { SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[24] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[25] } "NODE_NAME" } } } { "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.200 ns SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[26\] 11 COMB LC8_F16 2 " "Info: 11: + IC(0.000 ns) + CELL(0.200 ns) = 4.200 ns; Loc. = LC8_F16; Fanout = 2; COMB Node = 'SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[26\]'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "0.200 ns" { SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[25] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[26] } "NODE_NAME" } } } { "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.200 ns) 4.900 ns SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[27\] 12 COMB LC1_F18 2 " "Info: 12: + IC(0.500 ns) + CELL(0.200 ns) = 4.900 ns; Loc. = LC1_F18; Fanout = 2; COMB Node = 'SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[27\]'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "0.700 ns" { SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[26] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[27] } "NODE_NAME" } } } { "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 5.100 ns SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[28\] 13 COMB LC2_F18 2 " "Info: 13: + IC(0.000 ns) + CELL(0.200 ns) = 5.100 ns; Loc. = LC2_F18; Fanout = 2; COMB Node = 'SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[28\]'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "0.200 ns" { SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[27] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[28] } "NODE_NAME" } } } { "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 5.300 ns SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[29\] 14 COMB LC3_F18 2 " "Info: 14: + IC(0.000 ns) + CELL(0.200 ns) = 5.300 ns; Loc. = LC3_F18; Fanout = 2; COMB Node = 'SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[29\]'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "0.200 ns" { SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[28] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[29] } "NODE_NAME" } } } { "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 5.500 ns SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[30\] 15 COMB LC4_F18 1 " "Info: 15: + IC(0.000 ns) + CELL(0.200 ns) = 5.500 ns; Loc. = LC4_F18; Fanout = 1; COMB Node = 'SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|a_csnbuffer:result_node\|cout\[30\]'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "0.200 ns" { SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[29] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[30] } "NODE_NAME" } } } { "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "e:/eda/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 6.900 ns SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|unreg_res_node\[31\] 16 COMB LC5_F18 10 " "Info: 16: + IC(0.000 ns) + CELL(1.400 ns) = 6.900 ns; Loc. = LC5_F18; Fanout = 10; COMB Node = 'SubDDS:SubDDSi\|SRED:BusConversion2i\|AROUND:grnd_ur\|lpm_add_sub:i_rtl_1\|addcore:adder\|unreg_res_node\[31\]'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "1.400 ns" { SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[30] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|unreg_res_node[31] } "NODE_NAME" } } } { "e:/eda/libraries/megafunctions/addcore.tdf" "" "" { Text "e:/eda/libraries/megafunctions/addcore.tdf" 95 16 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(6.400 ns) 15.600 ns SubDDS:SubDDSi\|lpm_rom:LUTi\|altrom:srom\|q\[7\]~mem_cell_ra0 17 MEM EC9_E 1 " "Info: 17: + IC(2.300 ns) + CELL(6.400 ns) = 15.600 ns; Loc. = EC9_E; Fanout = 1; MEM Node = 'SubDDS:SubDDSi\|lpm_rom:LUTi\|altrom:srom\|q\[7\]~mem_cell_ra0'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "8.700 ns" { SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|unreg_res_node[31] SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[7]~mem_cell_ra0 } "NODE_NAME" } } } { "e:/eda/libraries/megafunctions/altrom.tdf" "" "" { Text "e:/eda/libraries/megafunctions/altrom.tdf" 82 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 17.000 ns SubDDS:SubDDSi\|lpm_rom:LUTi\|altrom:srom\|q\[7\] 18 MEM EC9_E 1 " "Info: 18: + IC(0.000 ns) + CELL(1.400 ns) = 17.000 ns; Loc. = EC9_E; Fanout = 1; MEM Node = 'SubDDS:SubDDSi\|lpm_rom:LUTi\|altrom:srom\|q\[7\]'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "1.400 ns" { SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[7]~mem_cell_ra0 SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[7] } "NODE_NAME" } } } { "e:/eda/libraries/megafunctions/altrom.tdf" "" "" { Text "e:/eda/libraries/megafunctions/altrom.tdf" 82 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(0.800 ns) 20.200 ns SubDDS:SubDDSi\|AltiMult:Product1i\|dataaint\[7\] 19 REG LC1_C18 9 " "Info: 19: + IC(2.400 ns) + CELL(0.800 ns) = 20.200 ns; Loc. = LC1_C18; Fanout = 9; REG Node = 'SubDDS:SubDDSi\|AltiMult:Product1i\|dataaint\[7\]'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "3.200 ns" { SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[7] SubDDS:SubDDSi|AltiMult:Product1i|dataaint[7] } "NODE_NAME" } } } { "d:/matlab6/DSPBuilder/Altlib/DSPBUILDER.VHD" "" "" { Text "d:/matlab6/DSPBuilder/Altlib/DSPBUILDER.VHD" 1268 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.300 ns 65.84 % " "Info: Total cell delay = 13.300 ns ( 65.84 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.900 ns 34.16 % " "Info: Total interconnect delay = 6.900 ns ( 34.16 % )" {  } {  } 0}  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "20.200 ns" { SubDDS:SubDDSi|SAdderSub:u9|result[17]~reg0 SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[17] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[18] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[19] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[20] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[21] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[22] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[23] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[24] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[25] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[26] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[27] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[28] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[29] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[30] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|unreg_res_node[31] SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[7]~mem_cell_ra0 SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[7] SubDDS:SubDDSi|AltiMult:Product1i|dataaint[7] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock clock to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clock 1 CLK Pin_55 83 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_55; Fanout = 83; CLK Node = 'clock'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "d:/matlab6/work/gw48_sopc_1c6_demo/dds_l/dds.vhd" "" "" { Text "d:/matlab6/work/gw48_sopc_1c6_demo/dds_l/dds.vhd" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns SubDDS:SubDDSi\|AltiMult:Product1i\|dataaint\[7\] 2 REG LC1_C18 9 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_C18; Fanout = 9; REG Node = 'SubDDS:SubDDSi\|AltiMult:Product1i\|dataaint\[7\]'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "0.400 ns" { clock SubDDS:SubDDSi|AltiMult:Product1i|dataaint[7] } "NODE_NAME" } } } { "d:/matlab6/DSPBuilder/Altlib/DSPBUILDER.VHD" "" "" { Text "d:/matlab6/DSPBuilder/Altlib/DSPBUILDER.VHD" 1268 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "2.400 ns" { clock SubDDS:SubDDSi|AltiMult:Product1i|dataaint[7] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.400 ns - Longest register " "Info: - Longest clock path from clock clock to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clock 1 CLK Pin_55 83 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_55; Fanout = 83; CLK Node = 'clock'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "d:/matlab6/work/gw48_sopc_1c6_demo/dds_l/dds.vhd" "" "" { Text "d:/matlab6/work/gw48_sopc_1c6_demo/dds_l/dds.vhd" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns SubDDS:SubDDSi\|SAdderSub:u9\|result\[17\]~reg0 2 REG LC1_F11 3 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_F11; Fanout = 3; REG Node = 'SubDDS:SubDDSi\|SAdderSub:u9\|result\[17\]~reg0'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "0.400 ns" { clock SubDDS:SubDDSi|SAdderSub:u9|result[17]~reg0 } "NODE_NAME" } } } { "d:/matlab6/DSPBuilder/Altlib/DSPBUILDER.VHD" "" "" { Text "d:/matlab6/DSPBuilder/Altlib/DSPBUILDER.VHD" 1481 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "2.400 ns" { clock SubDDS:SubDDSi|SAdderSub:u9|result[17]~reg0 } "NODE_NAME" } } }  } 0}  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "2.400 ns" { clock SubDDS:SubDDSi|AltiMult:Product1i|dataaint[7] } "NODE_NAME" } } } { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "2.400 ns" { clock SubDDS:SubDDSi|SAdderSub:u9|result[17]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "d:/matlab6/DSPBuilder/Altlib/DSPBUILDER.VHD" "" "" { Text "d:/matlab6/DSPBuilder/Altlib/DSPBUILDER.VHD" 1481 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "d:/matlab6/DSPBuilder/Altlib/DSPBUILDER.VHD" "" "" { Text "d:/matlab6/DSPBuilder/Altlib/DSPBUILDER.VHD" 1268 -1 0 } }  } 0}  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "20.200 ns" { SubDDS:SubDDSi|SAdderSub:u9|result[17]~reg0 SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[17] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[18] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[19] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[20] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[21] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[22] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[23] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[24] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[25] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[26] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[27] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[28] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[29] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cout[30] SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|unreg_res_node[31] SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[7]~mem_cell_ra0 SubDDS:SubDDSi|lpm_rom:LUTi|altrom:srom|q[7] SubDDS:SubDDSi|AltiMult:Product1i|dataaint[7] } "NODE_NAME" } } } { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "2.400 ns" { clock SubDDS:SubDDSi|AltiMult:Product1i|dataaint[7] } "NODE_NAME" } } } { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "2.400 ns" { clock SubDDS:SubDDSi|SAdderSub:u9|result[17]~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "SubDDS:SubDDSi\|AltiMult:Product1i\|databint\[0\] iAMPlifys\[0\] clock 6.600 ns register " "Info: tsu for register SubDDS:SubDDSi\|AltiMult:Product1i\|databint\[0\] (data pin = iAMPlifys\[0\], clock pin = clock) is 6.600 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.400 ns + Longest pin register " "Info: + Longest pin to register delay is 8.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns iAMPlifys\[0\] 1 PIN Pin_68 1 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = Pin_68; Fanout = 1; PIN Node = 'iAMPlifys\[0\]'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "" { iAMPlifys[0] } "NODE_NAME" } } } { "d:/matlab6/work/gw48_sopc_1c6_demo/dds_l/dds.vhd" "" "" { Text "d:/matlab6/work/gw48_sopc_1c6_demo/dds_l/dds.vhd" 34 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(0.800 ns) 8.400 ns SubDDS:SubDDSi\|AltiMult:Product1i\|databint\[0\] 2 REG LC7_C18 18 " "Info: 2: + IC(2.700 ns) + CELL(0.800 ns) = 8.400 ns; Loc. = LC7_C18; Fanout = 18; REG Node = 'SubDDS:SubDDSi\|AltiMult:Product1i\|databint\[0\]'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "3.500 ns" { iAMPlifys[0] SubDDS:SubDDSi|AltiMult:Product1i|databint[0] } "NODE_NAME" } } } { "d:/matlab6/DSPBuilder/Altlib/DSPBUILDER.VHD" "" "" { Text "d:/matlab6/DSPBuilder/Altlib/DSPBUILDER.VHD" 1268 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.700 ns 67.86 % " "Info: Total cell delay = 5.700 ns ( 67.86 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns 32.14 % " "Info: Total interconnect delay = 2.700 ns ( 32.14 % )" {  } {  } 0}  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "8.400 ns" { iAMPlifys[0] SubDDS:SubDDSi|AltiMult:Product1i|databint[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "d:/matlab6/DSPBuilder/Altlib/DSPBUILDER.VHD" "" "" { Text "d:/matlab6/DSPBuilder/Altlib/DSPBUILDER.VHD" 1268 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.400 ns - Shortest register " "Info: - Shortest clock path from clock clock to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clock 1 CLK Pin_55 83 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_55; Fanout = 83; CLK Node = 'clock'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "" { clock } "NODE_NAME" } } } { "d:/matlab6/work/gw48_sopc_1c6_demo/dds_l/dds.vhd" "" "" { Text "d:/matlab6/work/gw48_sopc_1c6_demo/dds_l/dds.vhd" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns SubDDS:SubDDSi\|AltiMult:Product1i\|databint\[0\] 2 REG LC7_C18 18 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC7_C18; Fanout = 18; REG Node = 'SubDDS:SubDDSi\|AltiMult:Product1i\|databint\[0\]'" {  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "0.400 ns" { clock SubDDS:SubDDSi|AltiMult:Product1i|databint[0] } "NODE_NAME" } } } { "d:/matlab6/DSPBuilder/Altlib/DSPBUILDER.VHD" "" "" { Text "d:/matlab6/DSPBuilder/Altlib/DSPBUILDER.VHD" 1268 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "2.400 ns" { clock SubDDS:SubDDSi|AltiMult:Product1i|databint[0] } "NODE_NAME" } } }  } 0}  } { { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "8.400 ns" { iAMPlifys[0] SubDDS:SubDDSi|AltiMult:Product1i|databint[0] } "NODE_NAME" } } } { "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" "" "" { Report "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "D:/MATLAB6/work/GW48_SOPC_1C6_DEMO/dds_L/db/dds.quartus_db" { Floorplan "" "" "2.400 ns" { clock SubDDS:SubDDSi|AltiMult:Product1i|databint[0] } "NODE_NAME" } } }  } 0}