📄 fdct.lst
字号:
695 000285 6F91 ADD *AR1+, 4, A ; + (16)*(X4)
000286 0C04
696 000287 6F91 ADD *AR1+, 4, A ; + (16)*(X5)
000288 0C04
697 000289 6F91 ADD *AR1+, 4, A ; + (16)*(X6)
00028a 0C04
698 00028b 6F81 ADD *AR1, 4, A ; + (16)*(X7)
00028c 0C04
699 00028d 8009- STL A, Y60 ; = Y60
700
701
702 00028e F071 RPTZ A, #7
00028f 0007
703 000290 7889 MACP *AR1-, COEF_F1, A
000291 0603+
704 000292 F464 SFTA A, 4
705 000293 6D91 MAR *AR1+ ; (64)[A*X0+B*X1+C*X2-D*X3-D*X4
706 000294 0002- ADD ROUND1, A ; -C*X5-B*X6-A*X7] + 4*ROUND1
707 000295 6F11- STH A, 2, Y61 ; = Y61
000296 0C62
708
709
710 000297 6F02- LD ROUND1, -4, A ; (ROUND1)/16
000298 0C5C
TMS320C54x COFF Assembler Beta Version 1.16 Thu Sep 19 16:41:10 1996
Copyright (c) 1996 Texas Instruments Incorporated
fdct.asm PAGE 18
711 000299 3001- LD E_P6, T
712 00029a 28B1 MAC *AR1+0, A ; + X0*E_P6
713 00029b 2C91 MAS *AR1+, A ; - X3*E_P6
714 00029c 2CB1 MAS *AR1+0, A ; - X4*E_P6
715 00029d 2889 MAC *AR1-, A ; + X7*E_P6
716 00029e 3000- LD F_P6, T
717 00029f 2889 MAC *AR1-, A ; + X6*F_P6
718 0002a0 2CA9 MAS *AR1-0, A ; - X5*F_P6
719 0002a1 2C89 MAS *AR1-, A ; - X2*F_P6
720 0002a2 2889 MAC *AR1-, A ; + X1*F_P6
721 0002a3 6F19- STH A, 6, Y62 ; Multiply prev summation by 16
0002a4 0C66
722 ; = Y62
723
724
725 0002a5 F071 RPTZ A, #7
0002a6 0007
726 0002a7 7891 MACP *AR1+, COEFF2, A ; 64(B*X0-D*X1-A*X2-C*X3+C*X4+A*X5
0002a8 060B+
727 0002a9 F464 SFTA A, 4
728 0002aa 6D89 MAR *AR1-
729 0002ab 0002- ADD ROUND1, A ; +D*X6-B*X7) + 4*ROUND1
730 0002ac 6F21- STH A, 2, Y63 ; = Y63
0002ad 0C62
731
732
733 0002ae 6F89 LD *AR1-, 4, A ; X7*16
0002af 0C44
734 0002b0 6F89 SUB *AR1-, 4, A ; - X6*16
0002b1 0C24
735 0002b2 6F89 SUB *AR1-, 4, A ; - X5*16
0002b3 0C24
736 0002b4 6F89 ADD *AR1-, 4, A ; + X4*16
0002b5 0C04
737 0002b6 6F89 ADD *AR1-, 4, A ; + X3*16
0002b7 0C04
738 0002b8 6F89 SUB *AR1-, 4, A ; - X2*16
0002b9 0C24
739 0002ba 6F89 SUB *AR1-, 4, A ; - X1*16
0002bb 0C24
740 0002bc 6F81 ADD *AR1, 4, A ; + X0*16
0002bd 0C04
741 0002be 8029- STL A, Y64 ; = Y64
742
743
744 0002bf F071 RPTZ A, #7
0002c0 0007
745 0002c1 7891 MACP *AR1+, COEFF3, A ; 8(D*X0-C*X1+B*X2-A*X3+A*X4-B*X5
0002c2 0613+
746 0002c3 F464 SFTA A, 4 ; +C*X6-D*X7)
747 0002c4 6D89 MAR *AR1-
748 0002c5 0002- ADD ROUND1, A ; + 4*ROUND1
749 0002c6 6F31- STH A, 2, Y65 ; = Y65
0002c7 0C62
750
TMS320C54x COFF Assembler Beta Version 1.16 Thu Sep 19 16:41:10 1996
Copyright (c) 1996 Texas Instruments Incorporated
fdct.asm PAGE 19
751
752 0002c8 6F02- LD ROUND1, -4, A ; (ROUND1)/16
0002c9 0C5C
753 0002ca 3000- LD F_P6, T
754 0002cb 28A9 MAC *AR1-0, A ; + F_P6*X7
755 0002cc 2C89 MAS *AR1-, A ; - F_P6*X4
756 0002cd 2CA9 MAS *AR1-0, A ; - F_P6*X3
757 0002ce 2891 MAC *AR1+, A ; + F_P6*X0
758 0002cf 3001- LD E_P6, T
759 0002d0 2C91 MAS *AR1+, A ; - E_P6*X1
760 0002d1 28B1 MAC *AR1+0, A ; + E_P6*X2
761 0002d2 2891 MAC *AR1+, A ; + E_P6*X5
762 0002d3 2C91 MAS *AR1+, A ; - E_P6*X6
763 0002d4 6F39- STH A, 6, Y66 ; Multiply prev summation by 16
0002d5 0C66
764 ; = Y66
765
766 0002d6 F071 RPTZ A, #7
0002d7 0007
767 0002d8 7889 MACP *AR1-, COEF_F4, A ; 64(D*X0-C*X1+B*X2-A*X3+A*X4-B*X5
0002d9 061B+
768 0002da F464 SFTA A, 4 ; +C*X6-D*X7)
769 0002db 6D91 MAR *AR1+
770 0002dc 0002- ADD ROUND1, A ; + 4*ROUND1
771 0002dd 6F41- STH A, 2, Y67 ; = Y67
0002de 0C62
772
773 0002df 6DE9 MAR *+AR1(8) ; Set AR1 to point to the next set
0002e0 0008
774 ; of 8 inputs
775
776 *********************************************************************
777 ; *
778 ; PROCESS EIGHTH 8 INPUTS. X(7,0)...X(7,7) -> Y(7,0)...Y(7,7) *
779 ; *
780 *********************************************************************
781
782 0002e1 6F91 LD *AR1+, 4, A ; + (16)*(X0)
0002e2 0C44
783 0002e3 6F91 ADD *AR1+, 4, A ; + (16)*(X1)
0002e4 0C04
784 0002e5 6F91 ADD *AR1+, 4, A ; + (16)*(X2)
0002e6 0C04
785 0002e7 6F91 ADD *AR1+, 4, A ; + (16)*(X3)
0002e8 0C04
786 0002e9 6F91 ADD *AR1+, 4, A ; + (16)*(X4)
0002ea 0C04
787 0002eb 6F91 ADD *AR1+, 4, A ; + (16)*(X5)
0002ec 0C04
788 0002ed 6F91 ADD *AR1+, 4, A ; + (16)*(X6)
0002ee 0C04
789 0002ef 6F81 ADD *AR1, 4, A ; + (16)*(X7)
0002f0 0C04
790 0002f1 800A- STL A, Y70 ; = Y70
791
TMS320C54x COFF Assembler Beta Version 1.16 Thu Sep 19 16:41:10 1996
Copyright (c) 1996 Texas Instruments Incorporated
fdct.asm PAGE 20
792
793 0002f2 F071 RPTZ A, #7
0002f3 0007
794 0002f4 7889 MACP *AR1-, COEF_F1, A
0002f5 0603+
795 0002f6 F464 SFTA A, 4
796 0002f7 6D91 MAR *AR1+ ; (64)[A*X0+B*X1+C*X2-D*X3-D*X4
797 0002f8 0002- ADD ROUND1, A ; -C*X5-B*X6-A*X7] + 4*ROUND1
798 0002f9 6F12- STH A, 2, Y71 ; = Y71
0002fa 0C62
799
800
801 0002fb 6F02- LD ROUND1, -4, A ; (ROUND1)/16
0002fc 0C5C
802 0002fd 3001- LD E_P6, T
803 0002fe 28B1 MAC *AR1+0, A ; + X0*E_P6
804 0002ff 2C91 MAS *AR1+, A ; - X3*E_P6
805 000300 2CB1 MAS *AR1+0, A ; - X4*E_P6
806 000301 2889 MAC *AR1-, A ; + X7*E_P6
807 000302 3000- LD F_P6, T
808 000303 2889 MAC *AR1-, A ; + X6*F_P6
809 000304 2CA9 MAS *AR1-0, A ; - X5*F_P6
810 000305 2C89 MAS *AR1-, A ; - X2*F_P6
811 000306 2889 MAC *AR1-, A ; + X1*F_P6
812 000307 6F1A- STH A, 6, Y72 ; Multiply prev summation by 16
000308 0C66
813 ; = Y72
814
815
816 000309 F071 RPTZ A, #7
00030a 0007
817 00030b 7891 MACP *AR1+, COEFF2, A ; 64(B*X0-D*X1-A*X2-C*X3+C*X4+A*X5
00030c 060B+
818 00030d F464 SFTA A, 4
819 00030e 6D89 MAR *AR1-
820 00030f 0002- ADD ROUND1, A ; +D*X6-B*X7) + 4*ROUND1
821 000310 6F22- STH A, 2, Y73 ; = Y73
000311 0C62
822
823
824 000312 6F89 LD *AR1-, 4, A ; X7*16
000313 0C44
825 000314 6F89 SUB *AR1-, 4, A ; - X6*16
000315 0C24
826 000316 6F89 SUB *AR1-, 4, A ; - X5*16
000317 0C24
827 000318 6F89 ADD *AR1-, 4, A ; + X4*16
000319 0C04
828 00031a 6F89 ADD *AR1-, 4, A ; + X3*16
00031b 0C04
829 00031c 6F89 SUB *AR1-, 4, A ; - X2*16
00031d 0C24
830 00031e 6F89 SUB *AR1-, 4, A ; - X1*16
00031f 0C24
831 000320 6F81 ADD *AR1, 4, A ; + X0*16
TMS320C54x COFF Assembler Beta Version 1.16 Thu Sep 19 16:41:10 1996
Copyright (c) 1996 Texas Instruments Incorporated
fdct.asm PAGE 21
000321 0C04
832 000322 802A- STL A, Y74 ; = Y74
833
834
835 000323 F071 RPTZ A, #7
000324 0007
836 000325 7891 MACP *AR1+, COEFF3, A ; 8(D*X0-C*X1+B*X2-A*X3+A*X4-B*X5
000326 0613+
837 000327 F464 SFTA A, 4 ; +C*X6-D*X7)
838 000328 6D89 MAR *AR1-
839 000329 0002- ADD ROUND1, A ; + 4*ROUND1
840 00032a 6F32- STH A, 2, Y75 ; = Y75
00032b 0C62
841
842
843 00032c 6F02- LD ROUND1, -4, A ; (ROUND1)/16
00032d 0C5C
844 00032e 3000- LD F_P6, T
845 00032f 28A9 MAC *AR1-0, A ; + F_P6*X7
846 000330 2C89 MAS *AR1-, A ; - F_P6*X4
847 000331 2CA9 MAS *AR1-0, A ; - F_P6*X3
848 000332 2891 MAC *AR1+, A ; + F_P6*X0
849 000333 3001- LD E_P6, T
850 000334 2C91 MAS *AR1+, A ; - E_P6*X1
851 000335 28B1 MAC *AR1+0, A ; + E_P6*X2
852 000336 2891 MAC *AR1+, A ; + E_P6*X5
853 000337 2C91 MAS *AR1+, A ; - E_P6*X6
854 000338 6F3A- STH A, 6, Y76 ; Multiply prev summation by 16
000339 0C66
855 ; = Y76
856
857 00033a F071 RPTZ A, #7
00033b 0007
858 00033c 7889 MACP *AR1-, COEF_F4, A ; 64(D*X0-C*X1+B*X2-A*X3+A*X4-B*X5
00033d 061B+
859 00033e F464⌨️ 快捷键说明
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