📄 fdct.lst
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525 0001cb 6F02- LD ROUND1, -4, A ; (ROUND1)/16
0001cc 0C5C
526 0001cd 3001- LD E_P6, T
527 0001ce 28B1 MAC *AR1+0, A ; + X0*E_P6
528 0001cf 2C91 MAS *AR1+, A ; - X3*E_P6
529 0001d0 2CB1 MAS *AR1+0, A ; - X4*E_P6
530 0001d1 2889 MAC *AR1-, A ; + X7*E_P6
531 0001d2 3000- LD F_P6, T
532 0001d3 2889 MAC *AR1-, A ; + X6*F_P6
533 0001d4 2CA9 MAS *AR1-0, A ; - X5*F_P6
534 0001d5 2C89 MAS *AR1-, A ; - X2*F_P6
535 0001d6 2889 MAC *AR1-, A ; + X1*F_P6
536 0001d7 6F17- STH A, 6, Y42 ; Multiply prev summation by 16
0001d8 0C66
537 ; = Y42
538
539
540 0001d9 F071 RPTZ A, #7
0001da 0007
541 0001db 7891 MACP *AR1+, COEFF2, A ; 64(B*X0-D*X1-A*X2-C*X3+C*X4+A*X5
0001dc 060B+
542 0001dd F464 SFTA A, 4
543 0001de 6D89 MAR *AR1-
544 0001df 0002- ADD ROUND1, A ; +D*X6-B*X7) + 4*ROUND1
545 0001e0 6F1F- STH A, 2, Y43 ; = Y43
0001e1 0C62
546
547
548 0001e2 6F89 LD *AR1-, 4, A ; X7*16
0001e3 0C44
549 0001e4 6F89 SUB *AR1-, 4, A ; - X6*16
0001e5 0C24
550 0001e6 6F89 SUB *AR1-, 4, A ; - X5*16
TMS320C54x COFF Assembler Beta Version 1.16 Thu Sep 19 16:41:10 1996
Copyright (c) 1996 Texas Instruments Incorporated
fdct.asm PAGE 14
0001e7 0C24
551 0001e8 6F89 ADD *AR1-, 4, A ; + X4*16
0001e9 0C04
552 0001ea 6F89 ADD *AR1-, 4, A ; + X3*16
0001eb 0C04
553 0001ec 6F89 SUB *AR1-, 4, A ; - X2*16
0001ed 0C24
554 0001ee 6F89 SUB *AR1-, 4, A ; - X1*16
0001ef 0C24
555 0001f0 6F81 ADD *AR1, 4, A ; + X0*16
0001f1 0C04
556 0001f2 8027- STL A, Y44 ; = Y44
557
558
559 0001f3 F071 RPTZ A, #7
0001f4 0007
560 0001f5 7891 MACP *AR1+, COEFF3, A ; 8(D*X0-C*X1+B*X2-A*X3+A*X4-B*X5
0001f6 0613+
561 0001f7 F464 SFTA A, 4 ; +C*X6-D*X7)
562 0001f8 6D89 MAR *AR1-
563 0001f9 0002- ADD ROUND1, A ; + 4*ROUND1
564 0001fa 6F2F- STH A, 2, Y45 ; = Y45
0001fb 0C62
565
566
567 0001fc 6F02- LD ROUND1, -4, A ; (ROUND1)/16
0001fd 0C5C
568 0001fe 3000- LD F_P6, T
569 0001ff 28A9 MAC *AR1-0, A ; + F_P6*X7
570 000200 2C89 MAS *AR1-, A ; - F_P6*X4
571 000201 2CA9 MAS *AR1-0, A ; - F_P6*X3
572 000202 2891 MAC *AR1+, A ; + F_P6*X0
573 000203 3001- LD E_P6, T
574 000204 2C91 MAS *AR1+, A ; - E_P6*X1
575 000205 28B1 MAC *AR1+0, A ; + E_P6*X2
576 000206 2891 MAC *AR1+, A ; + E_P6*X5
577 000207 2C91 MAS *AR1+, A ; - E_P6*X6
578 000208 6F37- STH A, 6, Y46 ; Multiply prev summation by 16
000209 0C66
579 ; = Y46
580
581 00020a F071 RPTZ A, #7
00020b 0007
582 00020c 7889 MACP *AR1-, COEF_F4, A ; 64(D*X0-C*X1+B*X2-A*X3+A*X4-B*X5
00020d 061B+
583 00020e F464 SFTA A, 4 ; +C*X6-D*X7)
584 00020f 6D91 MAR *AR1+
585 000210 0002- ADD ROUND1, A ; + 4*ROUND1
586 000211 6F3F- STH A, 2, Y47 ; = Y47
000212 0C62
587 000213 ERROR:
588 000213 6DE9 MAR *+AR1(8) ; Set AR1 to point to the next set
000214 0008
589 ; of 8 inputs
590 000215 F495 NOP
TMS320C54x COFF Assembler Beta Version 1.16 Thu Sep 19 16:41:10 1996
Copyright (c) 1996 Texas Instruments Incorporated
fdct.asm PAGE 15
591 000216 F495 NOP
592 000217 F495 NOP
593 000218 F495 NOP
594
595 *********************************************************************
596 ; *
597 ; PROCESS SIXTH 8 INPUTS. X(5,0)...X(5,7) -> Y(5,0)...Y(5,7) *
598 ; *
599 *********************************************************************
600
601 000219 6F91 LD *AR1+, 4, A ; + (16)*(X0)
00021a 0C44
602 00021b 6F91 ADD *AR1+, 4, A ; + (16)*(X1)
00021c 0C04
603 00021d 6F91 ADD *AR1+, 4, A ; + (16)*(X2)
00021e 0C04
604 00021f 6F91 ADD *AR1+, 4, A ; + (16)*(X3)
000220 0C04
605 000221 6F91 ADD *AR1+, 4, A ; + (16)*(X4)
000222 0C04
606 000223 6F91 ADD *AR1+, 4, A ; + (16)*(X5)
000224 0C04
607 000225 6F91 ADD *AR1+, 4, A ; + (16)*(X6)
000226 0C04
608 000227 6F81 ADD *AR1, 4, A ; + (16)*(X7)
000228 0C04
609 000229 8008- STL A, Y50 ; = Y50
610
611
612 00022a F071 RPTZ A, #7
00022b 0007
613 00022c 7889 MACP *AR1-, COEF_F1, A
00022d 0603+
614 00022e F464 SFTA A, 4
615 00022f 6D91 MAR *AR1+ ; (64)[A*X0+B*X1+C*X2-D*X3-D*X4
616 000230 0002- ADD ROUND1, A ; -C*X5-B*X6-A*X7] + 4*ROUND1
617 000231 6F10- STH A, 2, Y51 ; = Y51
000232 0C62
618
619
620 000233 6F02- LD ROUND1, -4, A ; (ROUND1)/16
000234 0C5C
621 000235 3001- LD E_P6, T
622 000236 28B1 MAC *AR1+0, A ; + X0*E_P6
623 000237 2C91 MAS *AR1+, A ; - X3*E_P6
624 000238 2CB1 MAS *AR1+0, A ; - X4*E_P6
625 000239 2889 MAC *AR1-, A ; + X7*E_P6
626 00023a 3000- LD F_P6, T
627 00023b 2889 MAC *AR1-, A ; + X6*F_P6
628 00023c 2CA9 MAS *AR1-0, A ; - X5*F_P6
629 00023d 2C89 MAS *AR1-, A ; - X2*F_P6
630 00023e 2889 MAC *AR1-, A ; + X1*F_P6
631 00023f 6F18- STH A, 6, Y52 ; Multiply prev summation by 16
000240 0C66
632 ; = Y52
TMS320C54x COFF Assembler Beta Version 1.16 Thu Sep 19 16:41:10 1996
Copyright (c) 1996 Texas Instruments Incorporated
fdct.asm PAGE 16
633
634
635 000241 F071 RPTZ A, #7
000242 0007
636 000243 7891 MACP *AR1+, COEFF2, A ; 64(B*X0-D*X1-A*X2-C*X3+C*X4+A*X5
000244 060B+
637 000245 F464 SFTA A, 4
638 000246 6D89 MAR *AR1-
639 000247 0002- ADD ROUND1, A ; +D*X6-B*X7) + 4*ROUND1
640 000248 6F20- STH A, 2, Y53 ; = Y53
000249 0C62
641
642
643 00024a 6F89 LD *AR1-, 4, A ; X7*16
00024b 0C44
644 00024c 6F89 SUB *AR1-, 4, A ; - X6*16
00024d 0C24
645 00024e 6F89 SUB *AR1-, 4, A ; - X5*16
00024f 0C24
646 000250 6F89 ADD *AR1-, 4, A ; + X4*16
000251 0C04
647 000252 6F89 ADD *AR1-, 4, A ; + X3*16
000253 0C04
648 000254 6F89 SUB *AR1-, 4, A ; - X2*16
000255 0C24
649 000256 6F89 SUB *AR1-, 4, A ; - X1*16
000257 0C24
650 000258 6F81 ADD *AR1, 4, A ; + X0*16
000259 0C04
651 00025a 8028- STL A, Y54 ; = Y54
652
653
654 00025b F071 RPTZ A, #7
00025c 0007
655 00025d 7891 MACP *AR1+, COEFF3, A ; 8(D*X0-C*X1+B*X2-A*X3+A*X4-B*X5
00025e 0613+
656 00025f F464 SFTA A, 4 ; +C*X6-D*X7)
657 000260 6D89 MAR *AR1-
658 000261 0002- ADD ROUND1, A ; + 4*ROUND1
659 000262 6F30- STH A, 2, Y55 ; = Y55
000263 0C62
660
661 000264 6F02- LD ROUND1, -4, A ; (ROUND1)/16
000265 0C5C
662 000266 3000- LD F_P6, T
663 000267 28A9 MAC *AR1-0, A ; + F_P6*X7
664 000268 2C89 MAS *AR1-, A ; - F_P6*X4
665 000269 2CA9 MAS *AR1-0, A ; - F_P6*X3
666 00026a 2891 MAC *AR1+, A ; + F_P6*X0
667 00026b 3001- LD E_P6, T
668 00026c 2C91 MAS *AR1+, A ; - E_P6*X1
669 00026d 28B1 MAC *AR1+0, A ; + E_P6*X2
670 00026e 2891 MAC *AR1+, A ; + E_P6*X5
671 00026f 2C91 MAS *AR1+, A ; - E_P6*X6
672 000270 6F38- STH A, 6, Y56 ; Multiply prev summation by 16
TMS320C54x COFF Assembler Beta Version 1.16 Thu Sep 19 16:41:10 1996
Copyright (c) 1996 Texas Instruments Incorporated
fdct.asm PAGE 17
000271 0C66
673 ; = Y56
674
675 000272 F071 RPTZ A, #7
000273 0007
676 000274 7889 MACP *AR1-, COEF_F4, A ; 64(D*X0-C*X1+B*X2-A*X3+A*X4-B*X5
000275 061B+
677 000276 F464 SFTA A, 4 ; +C*X6-D*X7)
678 000277 6D91 MAR *AR1+
679 000278 0002- ADD ROUND1, A ; + 4*ROUND1
680 000279 6F40- STH A, 2, Y57 ; = Y57
00027a 0C62
681
682 00027b 6DE9 MAR *+AR1(8) ; Set AR1 to point to the next set
00027c 0008
683 ; of 8 inputs
684
685 *********************************************************************
686 ; *
687 ; PROCESS SEVENTH 8 INPUTS. X(6,0)...X(6,7) -> Y(6,0)...Y(6,7) *
688 ; *
689 *********************************************************************
690
691 00027d 6F91 LD *AR1+, 4, A ; + (16)*(X0)
00027e 0C44
692 00027f 6F91 ADD *AR1+, 4, A ; + (16)*(X1)
000280 0C04
693 000281 6F91 ADD *AR1+, 4, A ; + (16)*(X2)
000282 0C04
694 000283 6F91 ADD *AR1+, 4, A ; + (16)*(X3)
000284 0C04
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