📄 fdct.lst
字号:
000114 060B+
359 000115 F464 SFTA A, 4
360 000116 6D89 MAR *AR1-
361 000117 0002- ADD ROUND1, A ; +D*X6-B*X7) + 4*ROUND1
362 000118 6F1D- STH A, 2, Y23 ; = Y23
000119 0C62
363
364
365 00011a 6F89 LD *AR1-, 4, A ; X7*16
00011b 0C44
366 00011c 6F89 SUB *AR1-, 4, A ; - X6*16
00011d 0C24
367 00011e 6F89 SUB *AR1-, 4, A ; - X5*16
00011f 0C24
368 000120 6F89 ADD *AR1-, 4, A ; + X4*16
000121 0C04
369 000122 6F89 ADD *AR1-, 4, A ; + X3*16
000123 0C04
370 000124 6F89 SUB *AR1-, 4, A ; - X2*16
000125 0C24
371 000126 6F89 SUB *AR1-, 4, A ; - X1*16
000127 0C24
372 000128 6F81 ADD *AR1, 4, A ; + X0*16
000129 0C04
373 00012a 8025- STL A, Y24 ; = Y24
374
375
376 00012b F071 RPTZ A, #7
00012c 0007
377 00012d 7891 MACP *AR1+, COEFF3, A ; 8(D*X0-C*X1+B*X2-A*X3+A*X4-B*X5
00012e 0613+
378 00012f F464 SFTA A, 4 ; +C*X6-D*X7)
379 000130 6D89 MAR *AR1-
380 000131 0002- ADD ROUND1, A ; + 4*ROUND1
381 000132 6F2D- STH A, 2, Y25 ; = Y25
000133 0C62
382
383
384 000134 6F02- LD ROUND1, -4, A ; (ROUND1)/16
000135 0C5C
385 000136 3000- LD F_P6, T
386 000137 28A9 MAC *AR1-0, A ; + F_P6*X7
TMS320C54x COFF Assembler Beta Version 1.16 Thu Sep 19 16:41:10 1996
Copyright (c) 1996 Texas Instruments Incorporated
fdct.asm PAGE 10
387 000138 2C89 MAS *AR1-, A ; - F_P6*X4
388 000139 2CA9 MAS *AR1-0, A ; - F_P6*X3
389 00013a 2891 MAC *AR1+, A ; + F_P6*X0
390 00013b 3001- LD E_P6, T
391 00013c 2C91 MAS *AR1+, A ; - E_P6*X1
392 00013d 28B1 MAC *AR1+0, A ; + E_P6*X2
393 00013e 2891 MAC *AR1+, A ; + E_P6*X5
394 00013f 2C91 MAS *AR1+, A ; - E_P6*X6
395 000140 6F35- STH A, 6, Y26 ; Multiply prev summation by 16
000141 0C66
396 ; = Y26
397
398 000142 F071 RPTZ A, #7
000143 0007
399 000144 7889 MACP *AR1-, COEF_F4, A ; 64(D*X0-C*X1+B*X2-A*X3+A*X4-B*X5
000145 061B+
400 000146 F464 SFTA A, 4 ; +C*X6-D*X7)
401 000147 6D91 MAR *AR1+
402 000148 0002- ADD ROUND1, A ; + 4*ROUND1
403 000149 6F3D- STH A, 2, Y27 ; = Y27
00014a 0C62
404
405 00014b 6DE9 MAR *+AR1(8) ; Set AR1 to point to the next set
00014c 0008
406 ; of 8 inputs
407
408 *********************************************************************
409 ; *
410 ; PROCESS FOURTH 8 INPUTS. X(3,0)...X(3,7) -> Y(3,0)...Y(3,7) *
411 ; *
412 *********************************************************************
413
414 00014d 6F91 LD *AR1+, 4, A ; + (16)*(X0)
00014e 0C44
415 00014f 6F91 ADD *AR1+, 4, A ; + (16)*(X1)
000150 0C04
416 000151 6F91 ADD *AR1+, 4, A ; + (16)*(X2)
000152 0C04
417 000153 6F91 ADD *AR1+, 4, A ; + (16)*(X3)
000154 0C04
418 000155 6F91 ADD *AR1+, 4, A ; + (16)*(X4)
000156 0C04
419 000157 6F91 ADD *AR1+, 4, A ; + (16)*(X5)
000158 0C04
420 000159 6F91 ADD *AR1+, 4, A ; + (16)*(X6)
00015a 0C04
421 00015b 6F81 ADD *AR1, 4, A ; + (16)*(X7)
00015c 0C04
422 00015d 8006- STL A, Y30 ; = Y30
423
424
425 00015e F071 RPTZ A, #7
00015f 0007
426 000160 7889 MACP *AR1-, COEF_F1, A
000161 0603+
TMS320C54x COFF Assembler Beta Version 1.16 Thu Sep 19 16:41:10 1996
Copyright (c) 1996 Texas Instruments Incorporated
fdct.asm PAGE 11
427 000162 F464 SFTA A, 4
428 000163 6D91 MAR *AR1+ ; (64)[A*X0+B*X1+C*X2-D*X3-D*X4
429 000164 0002- ADD ROUND1, A ; -C*X5-B*X6-A*X7] + 4*ROUND1
430 000165 6F0E- STH A, 2, Y31 ; = Y31
000166 0C62
431
432
433 000167 6F02- LD ROUND1, -4, A ; (ROUND1)/16
000168 0C5C
434 000169 3001- LD E_P6, T
435 00016a 28B1 MAC *AR1+0, A ; + X0*E_P6
436 00016b 2C91 MAS *AR1+, A ; - X3*E_P6
437 00016c 2CB1 MAS *AR1+0, A ; - X4*E_P6
438 00016d 2889 MAC *AR1-, A ; + X7*E_P6
439 00016e 3000- LD F_P6, T
440 00016f 2889 MAC *AR1-, A ; + X6*F_P6
441 000170 2CA9 MAS *AR1-0, A ; - X5*F_P6
442 000171 2C89 MAS *AR1-, A ; - X2*F_P6
443 000172 2889 MAC *AR1-, A ; + X1*F_P6
444 000173 6F16- STH A, 6, Y32 ; Multiply prev summation by 16
000174 0C66
445 ; = Y32
446
447
448 000175 F071 RPTZ A, #7
000176 0007
449 000177 7891 MACP *AR1+, COEFF2, A ; 64(B*X0-D*X1-A*X2-C*X3+C*X4+A*X5
000178 060B+
450 000179 F464 SFTA A, 4
451 00017a 6D89 MAR *AR1-
452 00017b 0002- ADD ROUND1, A ; +D*X6-B*X7) + 4*ROUND1
453 00017c 6F1E- STH A, 2, Y33 ; = Y33
00017d 0C62
454
455
456 00017e 6F89 LD *AR1-, 4, A ; X7*16
00017f 0C44
457 000180 6F89 SUB *AR1-, 4, A ; - X6*16
000181 0C24
458 000182 6F89 SUB *AR1-, 4, A ; - X5*16
000183 0C24
459 000184 6F89 ADD *AR1-, 4, A ; + X4*16
000185 0C04
460 000186 6F89 ADD *AR1-, 4, A ; + X3*16
000187 0C04
461 000188 6F89 SUB *AR1-, 4, A ; - X2*16
000189 0C24
462 00018a 6F89 SUB *AR1-, 4, A ; - X1*16
00018b 0C24
463 00018c 6F81 ADD *AR1, 4, A ; + X0*16
00018d 0C04
464 00018e 8026- STL A, Y34 ; = Y34
465
466
467 00018f F071 RPTZ A, #7
TMS320C54x COFF Assembler Beta Version 1.16 Thu Sep 19 16:41:10 1996
Copyright (c) 1996 Texas Instruments Incorporated
fdct.asm PAGE 12
000190 0007
468 000191 7891 MACP *AR1+, COEFF3, A ; 8(D*X0-C*X1+B*X2-A*X3+A*X4-B*X5
000192 0613+
469 000193 F464 SFTA A, 4 ; +C*X6-D*X7)
470 000194 6D89 MAR *AR1-
471 000195 0002- ADD ROUND1, A ; + 4*ROUND1
472 000196 6F2E- STH A, 2, Y35 ; = Y35
000197 0C62
473
474
475 000198 6F02- LD ROUND1, -4, A ; (ROUND1)/16
000199 0C5C
476 00019a 3000- LD F_P6, T
477 00019b 28A9 MAC *AR1-0, A ; + F_P6*X7
478 00019c 2C89 MAS *AR1-, A ; - F_P6*X4
479 00019d 2CA9 MAS *AR1-0, A ; - F_P6*X3
480 00019e 2891 MAC *AR1+, A ; + F_P6*X0
481 00019f 3001- LD E_P6, T
482 0001a0 2C91 MAS *AR1+, A ; - E_P6*X1
483 0001a1 28B1 MAC *AR1+0, A ; + E_P6*X2
484 0001a2 2891 MAC *AR1+, A ; + E_P6*X5
485 0001a3 2C91 MAS *AR1+, A ; - E_P6*X6
486 0001a4 6F36- STH A, 6, Y36 ; Multiply prev summation by 16
0001a5 0C66
487 ; = Y36
488
489 0001a6 F071 RPTZ A, #7
0001a7 0007
490 0001a8 7889 MACP *AR1-, COEF_F4, A ; 64(D*X0-C*X1+B*X2-A*X3+A*X4-B*X5
0001a9 061B+
491 0001aa F464 SFTA A, 4 ; +C*X6-D*X7)
492 0001ab 6D91 MAR *AR1+
493 0001ac 0002- ADD ROUND1, A ; + 4*ROUND1
494 0001ad 6F3E- STH A, 2, Y37 ; = Y37
0001ae 0C62
495
496 0001af 6DE9 MAR *+AR1(8) ; Set AR1 to point to the next set
0001b0 0008
497 ; of 8 inputs
498
499
500 *********************************************************************
501 ; *
502 ; PROCESS FIFTH 8 INPUTS. X(4,0)...X(4,7) -> Y(4,0)...Y(4,7) *
503 ; *
504 *********************************************************************
505
506 0001b1 6F91 LD *AR1+, 4, A ; + (16)*(X0)
0001b2 0C44
507 0001b3 6F91 ADD *AR1+, 4, A ; + (16)*(X1)
0001b4 0C04
508 0001b5 6F91 ADD *AR1+, 4, A ; + (16)*(X2)
0001b6 0C04
509 0001b7 6F91 ADD *AR1+, 4, A ; + (16)*(X3)
0001b8 0C04
TMS320C54x COFF Assembler Beta Version 1.16 Thu Sep 19 16:41:10 1996
Copyright (c) 1996 Texas Instruments Incorporated
fdct.asm PAGE 13
510 0001b9 6F91 ADD *AR1+, 4, A ; + (16)*(X4)
0001ba 0C04
511 0001bb 6F91 ADD *AR1+, 4, A ; + (16)*(X5)
0001bc 0C04
512 0001bd 6F91 ADD *AR1+, 4, A ; + (16)*(X6)
0001be 0C04
513 0001bf 6F81 ADD *AR1, 4, A ; + (16)*(X7)
0001c0 0C04
514 0001c1 8007- STL A, Y40 ; = Y40
515
516
517 0001c2 F071 RPTZ A, #7
0001c3 0007
518 0001c4 7889 MACP *AR1-, COEF_F1, A
0001c5 0603+
519 0001c6 F464 SFTA A, 4
520 0001c7 6D91 MAR *AR1+ ; (64)[A*X0+B*X1+C*X2-D*X3-D*X4
521 0001c8 0002- ADD ROUND1, A ; -C*X5-B*X6-A*X7] + 4*ROUND1
522 0001c9 6F0F- STH A, 2, Y41 ; = Y41
0001ca 0C62
523
524
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