📄 fdct.lst
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189 00005c 6F89 SUB *AR1-, 4, A ; - X2*16
00005d 0C24
190 00005e 6F89 SUB *AR1-, 4, A ; - X1*16
00005f 0C24
191 000060 6F81 ADD *AR1, 4, A ; + X0*16
000061 0C04
192 000062 8023- STL A, Y04 ; = Y04
193
194 000063 F071 RPTZ A, #7
000064 0007
195 000065 7891 MACP *AR1+, COEFF3, A ; 8(D*X0-C*X1+B*X2-A*X3+A*X4-B*X5
000066 0613+
196 000067 F464 SFTA A, 4 ; +C*X6-D*X7)
197 000068 6D89 MAR *AR1-
198 000069 0002- ADD ROUND1, A ; + 4*ROUND1
199 00006a 6F2B- STH A, 2, Y05 ; = Y05
00006b 0C62
200
201
202 00006c 6F02- LD ROUND1, -4, A ; (ROUND1)/16
00006d 0C5C
203 00006e 3000- LD F_P6, T
204 00006f 28A9 MAC *AR1-0, A ; + F_P6*X7
205 000070 2C89 MAS *AR1-, A ; - F_P6*X4
206 000071 2CA9 MAS *AR1-0, A ; - F_P6*X3
207 000072 2891 MAC *AR1+, A ; + F_P6*X0
208 000073 3001- LD E_P6, T
209 000074 2C91 MAS *AR1+, A ; - E_P6*X1
210 000075 28B1 MAC *AR1+0, A ; + E_P6*X2
211 000076 2891 MAC *AR1+, A ; + E_P6*X5
212 000077 2C91 MAS *AR1+, A ; - E_P6*X6
213 000078 6F33- STH A, 6, Y06 ; Multiply prev summation by 16
000079 0C66
214 ; = Y06
215
216 00007a F071 RPTZ A, #7
00007b 0007
217 00007c 7889 MACP *AR1-, COEF_F4, A ; 64(D*X0-C*X1+B*X2-A*X3+A*X4-B*X5
00007d 061B+
218 00007e F464 SFTA A, 4 ; +C*X6-D*X7)
219 00007f 6D91 MAR *AR1+
220 000080 0002- ADD ROUND1, A ; + 4*ROUND1
221 000081 6F3B- STH A, 2, Y07 ; = Y07
000082 0C62
222
223 000083 6DE9 MAR *+AR1(8) ; Set AR1 to point to the next set
000084 0008
224 ; of 8 inputs
225
226
227 *********************************************************************
TMS320C54x COFF Assembler Beta Version 1.16 Thu Sep 19 16:41:10 1996
Copyright (c) 1996 Texas Instruments Incorporated
fdct.asm PAGE 6
228 ; *
229 ; PROCESS SECOND 8 INPUTS. X(1,0)...X(1,7) -> Y(1,0)...Y(1,7) *
230 ; *
231 *********************************************************************
232
233 000085 6F91 LD *AR1+, 4, A ; + (16)*(X0)
000086 0C44
234 000087 6F91 ADD *AR1+, 4, A ; + (16)*(X1)
000088 0C04
235 000089 6F91 ADD *AR1+, 4, A ; + (16)*(X2)
00008a 0C04
236 00008b 6F91 ADD *AR1+, 4, A ; + (16)*(X3)
00008c 0C04
237 00008d 6F91 ADD *AR1+, 4, A ; + (16)*(X4)
00008e 0C04
238 00008f 6F91 ADD *AR1+, 4, A ; + (16)*(X5)
000090 0C04
239 000091 6F91 ADD *AR1+, 4, A ; + (16)*(X6)
000092 0C04
240 000093 6F81 ADD *AR1, 4, A ; + (16)*(X7)
000094 0C04
241 000095 8004- STL A, Y10 ; = Y10
242
243
244 000096 F071 RPTZ A, #7
000097 0007
245 000098 7889 MACP *AR1-, COEF_F1, A
000099 0603+
246 00009a F464 SFTA A, 4
247 00009b 6D91 MAR *AR1+ ; (64)[A*X0+B*X1+C*X2-D*X3-D*X4
248 00009c 0002- ADD ROUND1, A ; -C*X5-B*X6-A*X7] + 4*ROUND1
249 00009d 6F0C- STH A, 2, Y11 ; = Y11
00009e 0C62
250
251 00009f 6F02- LD ROUND1, -4, A ; (ROUND1)/16
0000a0 0C5C
252 0000a1 3001- LD E_P6, T
253 0000a2 28B1 MAC *AR1+0, A ; + X0*E_P6
254 0000a3 2C91 MAS *AR1+, A ; - X3*E_P6
255 0000a4 2CB1 MAS *AR1+0, A ; - X4*E_P6
256 0000a5 2889 MAC *AR1-, A ; + X7*E_P6
257 0000a6 3000- LD F_P6, T
258 0000a7 2889 MAC *AR1-, A ; + X6*F_P6
259 0000a8 2CA9 MAS *AR1-0, A ; - X5*F_P6
260 0000a9 2C89 MAS *AR1-, A ; - X2*F_P6
261 0000aa 2889 MAC *AR1-, A ; + X1*F_P6
262 0000ab 6F14- STH A, 6, Y12 ; Multiply prev summation by 16
0000ac 0C66
263 ; = Y12
264
265
266 0000ad F071 RPTZ A, #7
0000ae 0007
267 0000af 7891 MACP *AR1+, COEFF2, A ; 64(B*X0-D*X1-A*X2-C*X3+C*X4+A*X5
0000b0 060B+
TMS320C54x COFF Assembler Beta Version 1.16 Thu Sep 19 16:41:10 1996
Copyright (c) 1996 Texas Instruments Incorporated
fdct.asm PAGE 7
268 0000b1 F464 SFTA A, 4
269 0000b2 6D89 MAR *AR1-
270 0000b3 0002- ADD ROUND1, A ; +D*X6-B*X7) + 4*ROUND1
271 0000b4 6F1C- STH A, 2, Y13 ; = Y13
0000b5 0C62
272
273
274 0000b6 6F89 LD *AR1-, 4, A ; X7*16
0000b7 0C44
275 0000b8 6F89 SUB *AR1-, 4, A ; - X6*16
0000b9 0C24
276 0000ba 6F89 SUB *AR1-, 4, A ; - X5*16
0000bb 0C24
277 0000bc 6F89 ADD *AR1-, 4, A ; + X4*16
0000bd 0C04
278 0000be 6F89 ADD *AR1-, 4, A ; + X3*16
0000bf 0C04
279 0000c0 6F89 SUB *AR1-, 4, A ; - X2*16
0000c1 0C24
280 0000c2 6F89 SUB *AR1-, 4, A ; - X1*16
0000c3 0C24
281 0000c4 6F81 ADD *AR1, 4, A ; + X0*16
0000c5 0C04
282 0000c6 8024- STL A, Y14 ; = Y14
283
284
285 0000c7 F071 RPTZ A, #7
0000c8 0007
286 0000c9 7891 MACP *AR1+, COEFF3, A ; 8(D*X0-C*X1+B*X2-A*X3+A*X4-B*X5
0000ca 0613+
287 0000cb F464 SFTA A, 4 ; +C*X6-D*X7)
288 0000cc 6D89 MAR *AR1-
289 0000cd 0002- ADD ROUND1, A ; + 4*ROUND1
290 0000ce 6F2C- STH A, 2, Y15 ; = Y15
0000cf 0C62
291
292
293 0000d0 6F02- LD ROUND1, -4, A ; (ROUND1)/16
0000d1 0C5C
294 0000d2 3000- LD F_P6, T
295 0000d3 28A9 MAC *AR1-0, A ; + F_P6*X7
296 0000d4 2C89 MAS *AR1-, A ; - F_P6*X4
297 0000d5 2CA9 MAS *AR1-0, A ; - F_P6*X3
298 0000d6 2891 MAC *AR1+, A ; + F_P6*X0
299 0000d7 3001- LD E_P6, T
300 0000d8 2C91 MAS *AR1+, A ; - E_P6*X1
301 0000d9 28B1 MAC *AR1+0, A ; + E_P6*X2
302 0000da 2891 MAC *AR1+, A ; + E_P6*X5
303 0000db 2C91 MAS *AR1+, A ; - E_P6*X6
304 0000dc 6F34- STH A, 6, Y16 ; Multiply prev summation by 16
0000dd 0C66
305 ; = Y16
306
307 0000de F071 RPTZ A, #7
0000df 0007
TMS320C54x COFF Assembler Beta Version 1.16 Thu Sep 19 16:41:10 1996
Copyright (c) 1996 Texas Instruments Incorporated
fdct.asm PAGE 8
308 0000e0 7889 MACP *AR1-, COEF_F4, A ; 64(D*X0-C*X1+B*X2-A*X3+A*X4-B*X5
0000e1 061B+
309 0000e2 F464 SFTA A, 4 ; +C*X6-D*X7)
310 0000e3 6D91 MAR *AR1+
311 0000e4 0002- ADD ROUND1, A ; + 4*ROUND1
312 0000e5 6F3C- STH A, 2, Y17 ; = Y17
0000e6 0C62
313
314 0000e7 6DE9 MAR *+AR1(8) ; Set AR1 to point to the next set
0000e8 0008
315 ; of 8 inputs
316
317 *********************************************************************
318 ; *
319 ; PROCESS THIRD 8 INPUTS. X(2,0)...X(2,7) -> Y(2,0)...Y(2,7) *
320 ; *
321 *********************************************************************
322
323 0000e9 6F91 LD *AR1+, 4, A ; + (16)*(X0)
0000ea 0C44
324 0000eb 6F91 ADD *AR1+, 4, A ; + (16)*(X1)
0000ec 0C04
325 0000ed 6F91 ADD *AR1+, 4, A ; + (16)*(X2)
0000ee 0C04
326 0000ef 6F91 ADD *AR1+, 4, A ; + (16)*(X3)
0000f0 0C04
327 0000f1 6F91 ADD *AR1+, 4, A ; + (16)*(X4)
0000f2 0C04
328 0000f3 6F91 ADD *AR1+, 4, A ; + (16)*(X5)
0000f4 0C04
329 0000f5 6F91 ADD *AR1+, 4, A ; + (16)*(X6)
0000f6 0C04
330 0000f7 6F81 ADD *AR1, 4, A ; + (16)*(X7)
0000f8 0C04
331 0000f9 8005- STL A, Y20 ; = Y20
332
333
334 0000fa F071 RPTZ A, #7
0000fb 0007
335 0000fc 7889 MACP *AR1-, COEF_F1, A
0000fd 0603+
336 0000fe F464 SFTA A, 4
337 0000ff 6D91 MAR *AR1+ ; (64)[A*X0+B*X1+C*X2-D*X3-D*X4
338 000100 0002- ADD ROUND1, A ; -C*X5-B*X6-A*X7] + 4*ROUND1
339 000101 6F0D- STH A, 2, Y21 ; = Y21
000102 0C62
340
341
342 000103 6F02- LD ROUND1, -4, A ; (ROUND1)/16
000104 0C5C
343 000105 3001- LD E_P6, T
344 000106 28B1 MAC *AR1+0, A ; + X0*E_P6
345 000107 2C91 MAS *AR1+, A ; - X3*E_P6
346 000108 2CB1 MAS *AR1+0, A ; - X4*E_P6
347 000109 2889 MAC *AR1-, A ; + X7*E_P6
TMS320C54x COFF Assembler Beta Version 1.16 Thu Sep 19 16:41:10 1996
Copyright (c) 1996 Texas Instruments Incorporated
fdct.asm PAGE 9
348 00010a 3000- LD F_P6, T
349 00010b 2889 MAC *AR1-, A ; + X6*F_P6
350 00010c 2CA9 MAS *AR1-0, A ; - X5*F_P6
351 00010d 2C89 MAS *AR1-, A ; - X2*F_P6
352 00010e 2889 MAC *AR1-, A ; + X1*F_P6
353 00010f 6F15- STH A, 6, Y22 ; Multiply prev summation by 16
000110 0C66
354 ; = Y22
355
356
357 000111 F071 RPTZ A, #7
000112 0007
358 000113 7891 MACP *AR1+, COEFF2, A ; 64(B*X0-D*X1-A*X2-C*X3+C*X4+A*X5
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