📄 fdct.lst
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TMS320C54x COFF Assembler Beta Version 1.16 Thu Sep 19 16:41:10 1996
Copyright (c) 1996 Texas Instruments Incorporated
fdct.asm PAGE 1
1 ***************************************************************
2 * (C) COPYRIGHT TEXAS INSTRUMENTS, INC. 1996 *
3 ***************************************************************
4 * FILE NAME: FDCT.ASM *
5 * *
6 * HISTORY: This program is originally written in TMS320C5x *
7 * assembly language by G. Peake of Texas *
8 * Instruments, Inc. *
9 * *
10 * TRANSLATORS: Rushani Wirasinghe *
11 * Xiaozhen Zhang *
12 * *
13 * DESCRIPTION: *
14 * - Forward DCT algorithm. *
15 * - Code written in TMS320C54x assembly language. *
16 * - Files: Fdct.asm (This file) *
17 * Dct.doc (DCT Documentation) *
18 * fdct.cmd (Linker Command File) *
19 * Fdct_dat.inc *
20 * - Import Functions: none *
21 * - Import Data: none *
22 * - Export Functions: none *
23 * - Export Data: none *
24 * *
25 * LAST DAY MODIFIED: August 23, 1996 *
26 ***************************************************************
27
28 .mmregs
29
30 .def entry
31
32 000000 .sect "INIT"
33 *
34 * Initialise
35 *
36 000000 F495 entry NOP
37 000001 F495 NOP
38 000002 F7B8 SSBX SXM ; set sign extension mode
39 000003 F7B9 SSBX OVM ; enable saturation
40 000004 EA00 LD #0, DP ; set data page
41 000005 771D STM 0FFE0h, PMST ; Init PMST reg.
000006 FFE0
42 * ||||| | ||||||
43 * ----+ | |||||+- BRAF - reset block RPT active
44 * | | ||||+-- TRM - C5X T-reg mode
45 * | | |||+--- NDX - C5x Index reg mode
46 * | | ||+---- MP/MC - MC mode
47 * | | |+----- RAM - SPRAM = @prog
48 * | | +------ OVLY - SPRAM = @data
49 * | +-------- AVIS - no addr line visibility
50 * +------------ IPTR - Interrupt vectors at 000h
51 *
52
53 000007 F6B6 RSBX FRCT
54
TMS320C54x COFF Assembler Beta Version 1.16 Thu Sep 19 16:41:10 1996
Copyright (c) 1996 Texas Instruments Incorporated
fdct.asm PAGE 2
55 .include "fdct_dat.inc" ; FDCT data storage declaration
56
57
58 0001 MODE .SET 1 ; MODE=1 TEST ON SIMULATOR
59
60 0000 PAGE0 .SET 0
61 0004 PAGE4 .SET 4
62 0018 PAGE24 .SET 24d
63 0019 PAGE25 .SET 25d
64
65 0200 B0 .SET 0200h
66 0300 B1 .SET 0300h
67 0060 B2 .SET 060h
68
69 0001 PA1BIS .SET 1
70 0002 PA2BIS .SET 2
71 0003 PA3BIS .SET 3
72 0004 PA4BIS .SET 4
73 0005 PA5BIS .SET 5
74 0006 PA6BIS .SET 6
75
76
77 * Initialization of the registers
78
79 000000 .sect "FDCT"
80
81 000000 EA18 INIT LD #PAGE24, DP
82 000001 7601- ST #21407, E_P6
000002 539F
83 000003 7600- ST #8867, F_P6
000004 22A3
84 000005 7602- ST #2000H, ROUND1
000006 2000
85
86 000007 EA19 TBL: LD #PAGE25, DP
87 000008 7643- ST #21407, E_P7
000009 539F
88 00000a 7644- ST #8867, F_P7
00000b 22A3
89 00000c 7645- ST #4000H, ROUND2
00000d 4000
90 00000e 7646- ST #40H, ROUND3
00000f 0040
91
92
93
94 000010 START
95
96 ***********************************************************************
97 * READ A 8x8 BLOCK AND PLACE IT IN X(M,N) *
98 * *
99 ***********************************************************************
100
101 * WE CONSIDER THAT WE HAVE TO TREAT ONE IMAGE CONSTITUTED OF 1584
102 * BLOCKS OF 64 PIXELS: ONE ROW= 352 PIXELS; ONE COLUMN= 288 PIXELS.
TMS320C54x COFF Assembler Beta Version 1.16 Thu Sep 19 16:41:10 1996
Copyright (c) 1996 Texas Instruments Incorporated
fdct.asm PAGE 3
103
104
105 * IF MODE = SIMULATOR
106
107 .IF MODE=1
108 000010 7710 STM #63, AR0 ; AR0= # of inputs to be taken - 1
000011 003F
109 000012 7711 STM #X, AR1 ; AR1= address of first input
000013 0043-
110 000014 7491 BEG PORTR #PA1BIS, *AR1+ ; Read and store to addr(AR1)
000015 0001
111 000016 6C88 BANZ BEG, *AR0- ; Repeat above code 64 times
000017 0014+
112 ; till all 64 pixels are read
113
114 .ENDIF
115
116
117 ; ******************************************
118 ; * *
119 ; * FIRST STEP : *
120 ; * *
121 ; * CALCULATE INNER TRANSFORM *
122 ; * (PROCESS INPUT ROWS) *
123 ; * *
124 ; ******************************************
125
126
127 000018 7710 STM #3, AR0
000019 0003
128 00001a 7711 STM #X, AR1 ; Reset AR1 to first input
00001b 0043-
129 00001c 7712 STM #Y00, AR2 ; Set AR2 to first Y block
00001d 0003-
130
131
132 *********************************************************************
133 ; *
134 ; PROCESS FIRST 8 INPUTS. X(0,0)...X(0,7) -> Y(0,0)...Y(0,7) *
135 ; *
136 *********************************************************************
137
138 00001e F495 DCT1 NOP
139 00001f F495 NOP
140 000020 EA18 LD #PAGE24, DP
141 000021 6F91 LD *AR1+, 4, A ; + (16)*(X0)
000022 0C44
142 000023 6F91 ADD *AR1+, 4, A ; + (16)*(X1)
000024 0C04
143 000025 6F91 ADD *AR1+, 4, A ; + (16)*(X2)
000026 0C04
144 000027 6F91 ADD *AR1+, 4, A ; + (16)*(X3)
000028 0C04
145 000029 6F91 ADD *AR1+, 4, A ; + (16)*(X4)
00002a 0C04
TMS320C54x COFF Assembler Beta Version 1.16 Thu Sep 19 16:41:10 1996
Copyright (c) 1996 Texas Instruments Incorporated
fdct.asm PAGE 4
146 00002b 6F91 ADD *AR1+, 4, A ; + (16)*(X5)
00002c 0C04
147 00002d 6F91 ADD *AR1+, 4, A ; + (16)*(X6)
00002e 0C04
148 00002f 6F81 ADD *AR1, 4,A ; + (16)*(X7)
000030 0C04
149 000031 8003- STL A, Y00 ; = Y00
150
151
152 000032 F071 RPTZ A, #7
000033 0007
153 000034 7889 MACP *AR1-, COEF_F1, A
000035 0603+
154 000036 F464 SFTA A, 4
155 000037 6D91 MAR *AR1+ ; (64)[A*X0+B*X1+C*X2-D*X3-D*X4
156 000038 0002- ADD ROUND1, A ; -C*X5-B*X6-A*X7] + 4*ROUND1
157 000039 6F0B- STH A, 2, Y01 ; = Y01
00003a 0C62
158
159
160 00003b 6F02- LD ROUND1, -4, A ; (ROUND1)/16
00003c 0C5C
161 00003d 3001- LD E_P6, T
162 00003e 28B1 MAC *AR1+0, A ; + X0*E_P6
163 00003f 2C91 MAS *AR1+, A ; - X3*E_P6
164 000040 2CB1 MAS *AR1+0, A ; - X4*E_P6
165 000041 2889 MAC *AR1-, A ; + X7*E_P6
166 000042 3000- LD F_P6, T
167 000043 2889 MAC *AR1-, A ; + X6*F_P6
168 000044 2CA9 MAS *AR1-0, A ; - X5*F_P6
169 000045 2C89 MAS *AR1-, A ; - X2*F_P6
170 000046 2889 MAC *AR1-, A ; + X1*F_P6
171 000047 6F13- STH A, 6, Y02 ; Multiply prev summation by 16
000048 0C66
172 ; = Y02
173
174 000049 F071 RPTZ A, #7
00004a 0007
175 00004b 7891 MACP *AR1+, COEFF2, A ; 64(B*X0-D*X1-A*X2-C*X3+C*X4+A*X5
00004c 060B+
176 00004d F464 SFTA A, 4
177 00004e 6D89 MAR *AR1-
178 00004f 0002- ADD ROUND1, A ; +D*X6-B*X7) + 4*ROUND1
179 000050 6F1B- STH A, 2, Y03 ; = Y03
000051 0C62
180
181
182
183 000052 6F89 LD *AR1-, 4, A ; X7*16
000053 0C44
184
185 000054 6F89 SUB *AR1-, 4, A ; - X6*16
000055 0C24
186 000056 6F89 SUB *AR1-, 4, A ; - X5*16
000057 0C24
TMS320C54x COFF Assembler Beta Version 1.16 Thu Sep 19 16:41:10 1996
Copyright (c) 1996 Texas Instruments Incorporated
fdct.asm PAGE 5
187 000058 6F89 ADD *AR1-, 4, A ; + X4*16
000059 0C04
188 00005a 6F89 ADD *AR1-, 4, A ; + X3*16
00005b 0C04
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