m.vhd

来自「这是一个简单m序列」· VHDL 代码 · 共 105 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY m IS
  PORT(clk:IN STD_LOGIC;
       M_Sel:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
       M_out:OUT STD_LOGIC);
END m;
ARCHITECTURE behave OF m IS
  SIGNAL reg7:STD_LOGIC_VECTOR(6 DOWNTO 0);
      
BEGIN
  PROCESS(clk)
         BEGIN 
            IF CLK'EVENT AND CLK='1'  THEN
           

            if  M_Sel="00" then  
             if 
                 reg7="000" 
             THEN
                 reg7(6)<='1';
            else 
              reg7(5 DOWNTO 4)<=reg7(6 DOWNTO 5);
              reg7(6)<=reg7(4) XOR reg7(5);                        
           
             END IF;
          
            

           elsif M_Sel="01" then
             if reg7="0000" THEN 
             reg7(6)<='1';
             else  
              reg7(6)<=reg7(3) XOR reg7(4);                        
              reg7(5 DOWNTO 3)<=reg7(6 DOWNTO 4);
             
             end if; 
           
            elsif M_Sel="10" then  
              if reg7="000000" THEN 
             reg7(6)<='1';
             else  
              reg7(6)<=reg7(1) XOR reg7(2);                        
              reg7(5 DOWNTO 1)<=reg7(6 DOWNTO 2);
             
            end if;

            else   
               if reg7="0000000" THEN 
             reg7(6)<='1';
             else  
              reg7(6)<=reg7(0) XOR reg7(1);                        
              reg7(5 DOWNTO 0)<=reg7(6 DOWNTO 1);
              
            end if;
            
           END IF;
          M_out<=reg7(6);
      end if;
    END PROCESS;
        
    END  behave;