📄 m.rpt
字号:
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: i:\kcsg\m\a\m.rpt
m
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 10/ 48( 20%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: i:\kcsg\m\a\m.rpt
m
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: i:\kcsg\m\a\m.rpt
m
** EQUATIONS **
clk : INPUT;
M_Sel0 : INPUT;
M_Sel1 : INPUT;
-- Node name is 'M_out'
-- Equation name is 'M_out', type is output
M_out = _LC5_A15;
-- Node name is ':12' = 'reg70'
-- Equation name is 'reg70', location is LC7_A15, type is buried.
reg70 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = M_Sel0 & M_Sel1 & reg71
# !M_Sel1 & reg70
# !M_Sel0 & reg70;
-- Node name is ':11' = 'reg71'
-- Equation name is 'reg71', location is LC8_A15, type is buried.
reg71 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !M_Sel1 & reg71
# M_Sel1 & reg72;
-- Node name is ':10' = 'reg72'
-- Equation name is 'reg72', location is LC2_A15, type is buried.
reg72 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !M_Sel1 & reg72
# M_Sel1 & reg73;
-- Node name is ':9' = 'reg73'
-- Equation name is 'reg73', location is LC1_A21, type is buried.
reg73 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !M_Sel0 & !M_Sel1 & reg73
# M_Sel1 & reg74
# M_Sel0 & reg74;
-- Node name is ':8' = 'reg74'
-- Equation name is 'reg74', location is LC1_A15, type is buried.
reg74 = DFFE( reg75, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':7' = 'reg75'
-- Equation name is 'reg75', location is LC6_A15, type is buried.
reg75 = DFFE( reg76, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':6' = 'reg76'
-- Equation name is 'reg76', location is LC3_A21, type is buried.
reg76 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC7_A21 & M_Sel1
# _LC7_A21 & M_Sel0
# _LC8_A21 & !M_Sel0 & !M_Sel1;
-- Node name is ':4'
-- Equation name is '_LC5_A15', type is buried
_LC5_A15 = DFFE( reg76, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '~144~1'
-- Equation name is '~144~1', location is LC3_A15, type is buried.
-- synthesized logic cell
_LC3_A15 = LCELL( _EQ006);
_EQ006 = !reg70 & !reg71 & !reg72 & !reg75;
-- Node name is ':144'
-- Equation name is '_LC2_A21', type is buried
_LC2_A21 = LCELL( _EQ007);
_EQ007 = _LC3_A15 & !reg73 & !reg74 & !reg76;
-- Node name is ':332'
-- Equation name is '_LC8_A21', type is buried
_LC8_A21 = LCELL( _EQ008);
_EQ008 = _LC2_A21
# reg74 & !reg75
# !reg74 & reg75;
-- Node name is ':563'
-- Equation name is '_LC6_A21', type is buried
_LC6_A21 = LCELL( _EQ009);
_EQ009 = !reg73 & reg74
# reg73 & !reg74
# _LC2_A21;
-- Node name is ':803'
-- Equation name is '_LC4_A21', type is buried
_LC4_A21 = LCELL( _EQ010);
_EQ010 = reg71 & !reg72
# !reg71 & reg72
# _LC2_A21;
-- Node name is ':1055'
-- Equation name is '_LC4_A15', type is buried
_LC4_A15 = LCELL( _EQ011);
_EQ011 = !reg70 & reg71
# reg70 & !reg71
# _LC2_A21;
-- Node name is ':1116'
-- Equation name is '_LC7_A21', type is buried
_LC7_A21 = LCELL( _EQ012);
_EQ012 = _LC5_A21
# _LC6_A21 & M_Sel0 & !M_Sel1;
-- Node name is ':1118'
-- Equation name is '_LC5_A21', type is buried
_LC5_A21 = LCELL( _EQ013);
_EQ013 = _LC4_A21 & !M_Sel0 & M_Sel1
# _LC4_A15 & !M_Sel0 & !M_Sel1
# _LC4_A15 & M_Sel0 & M_Sel1;
Project Information i:\kcsg\m\a\m.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:07
Timing SNF Extractor 00:00:01
Assembler 00:00:03
-------------------------- --------
Total Time 00:00:13
Memory Allocated
-----------------
Peak memory allocated during compilation = 9,859K
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