hcd_1161.h

isp116x系列USB芯片在LINUX下的驱动程序

#define 	HC_ED_SKIP						0x00004000UL			/* Skip this ED */
#define 	HC_ED_F							0x00008000UL			/* Format of this ED */
#define 	HC_ED_MPS						0x07FF0000UL			/* Maximum Packet Size */

/* Bit field definition for hwHeadP of the ed_t */
#define 	HC_ED_TOGGLE					0x00000002UL			/* Bit 1, toggle carry */
#define 	HC_ED_HALTED					0x00000001UL			/* Bit 0, halted */


#define 	OHCI_SETUP						0X00000000UL
#define 	OHCI_OUT						0x00000001UL
#define 	OHCI_IN							0x00000002UL



/*-----------------------------------------------------------*/
/* 1161 control and data port numbers */
/*-----------------------------------------------------------*/

#define		HC_IO_BASE						0x290
#define		HC_DATA							HC_IO_BASE
#define		HC_COM							(HC_IO_BASE+2)

#define		HC_IO_SIZE						(HC_COM - HC_DATA +1)

#define 	IRQ4HC_CHNNL            		10						/* ISP1161 host controller's IRQ line */

/*-----------------------------------------------------------*/
/* ISP1161 host controller operational registers */
/*-----------------------------------------------------------*/

#define 	uHcRevision                     0x00UL			/* Revision Register */
#define 	uHcControl                      0x01UL			/* Control Register */
#define 	uHcCommandStatus                0x02UL			/* Command Status Register */
#define 	uHcInterruptStatus              0x03UL			/* Interrupt Status Register */
#define 	uHcInterruptEnable              0x04UL			/* Interrupt Enable Register */
#define 	uHcInterruptDisable             0x05UL			/* Interrupt Disable Register */
#define 	uHcFmInterval                   0x0dUL			/* Frame Interval Register */
#define 	uHcFmRemaining                  0x0eUL			/* Frame Remaining Register */
#define 	uHcFmNumber                     0x0fUL			/* Frame Number Register */
#define 	uHcLsThreshold                  0x11UL			/* Threshold register */
#define 	uHcRhDescriptorA                0x12UL			/* Root Hub Descriptor A Register */
#define 	uHcRhDescriptorB                0x13UL			/* Root Hub Descriptor B Register */
#define 	uHcRhStatus                     0x14UL			/* Root Hub Status Register */
#define 	uHcRhPort1Status                0x15UL          /* Root Hub Port 1 status */  /* ISP1161 has only two root hub ports */
#define 	uHcRhPort2Status                0x16UL			/* Root Hub Port 2 status */ 

/* These two registers are used internally by software. They are not ISP1161 hardware 
	registers.*/
#define 	uHcHcdControl                   0x17UL			/* HCD Software Control Register */
#define 	uHcHcdCommandStatus             0x18UL			/* HCD Software Command Status Register */


/* Bit field definition for register HcCommandStatus */
#define HC_COMMAND_STATUS_HCR		0x00000001UL		/* Host Controller Reset */
#define HC_COMMAND_STATUS_CLF		0x00000002UL		/* Control List Filled   */
#define HC_COMMAND_STATUS_BLF		0x00000004UL		/* Bulk List Filled      */



/**********************/
/* HcControl Register */
/**********************/
#define CB_RATIO				3	/* Control/Bulk transfer ratio */
									/* 0 = 1:1                     */
									/* 1 = 2:1                     */
									/* 2 = 3:1                     */
									/* 3 = 4:1                     */

#define PERIODIC_LIST_ENABLE	YES	/* Periodic transfer enable    */
#define ISO_ENABLE				YES	/* Isochronous transfer enable */
#define CONTROL_LIST_ENABLE		YES	/* Control transfer enable     */
#define BULK_LIST_ENABLE		YES	/* Bulk transfer enable        */
#define HC_STATE				2	/* Host functional state */
									/* 0 = Reset             */
									/* 1 = Resume            */
									/* 2 = Operational       */
									/* 3 = Suspend           */

#define REMOTE_WAKEUP_CONN		NO	/* Remote wakeup connected */

#define REMOTE_WAKEUP_ENABLE	NO	/* Remote wakeup enable    */



/* Bit field definition for register HcControl */
#define HC_CONTROL_HCFS				0x000000C0UL		/* Host Controller Functional State, bit 7..6 */
#define HC_CONTROL_RWC				0x00000200UL		/* Remote Wakeup Connected, bit 9 */
#define HC_CONTROL_RWE				0x00000400UL		/* Remote Wakeup Enable, bit 10 */

/* Bit field definition for HCD register HcHcdControl */
/* ISP1161 does not have this HC register as OHCI     */
/* It is added as a global variable to emulate the    */
/* OHCI transfer control functionality defined in the */
/* following bit field                                */
#define HC_CONTROL_CBSR				0x00000003UL		/* Control/Bulk ratio */
#define HC_CONTROL_PLE				0X00000004UL		/* Periodic List Enable */
#define HC_CONTROL_IE				0x00000008UL		/* Isochronous Enable */
#define HC_CONTROL_CLE				0x00000010UL		/* Control List Enable */
#define HC_CONTROL_BLE				0x00000020UL		/* Bulk List Enable */
#define HC_CONTROL_TIP				0x00000100UL		/* Transfer In Progress */

/* Bit field definition for HCD register HcHcdCommand. */
/* ISP1161 does not have this register. This register  */
/* is added as an HCD global variable to emulate the   */
/* OHCI transfer control functionality                 */
#define HC_COMMAND_STATUS_CLF		0x00000002UL		/* Control List Filled   */
#define HC_COMMAND_STATUS_BLF		0x00000004UL		/* Bulk List Filled      */

/* Bit field definition for register HcInterruptStatus */
/* HcInterruptEnable/HcInterruptDisable registers      */
#define HC_INTERRUPT_SO				0x00000001UL			/* Scheduling Overrun      */
#define HC_INTERRUPT_SF				0x00000004UL			/* Start of Frame          */
#define HC_INTERRUPT_RD				0x00000008UL			/* Resume Detect           */
#define HC_INTERRUPT_UE				0x00000010UL			/* Unrecoverable error     */
#define HC_INTERRUPT_FNO			0x00000020UL			/* Frame Number Overflow   */
#define HC_INTERRUPT_RHSC			0x00000040UL			/* Root Hub Status Change  */
#define HC_INTERRUPT_MIE			0x80000000UL			/* Master Interrupt Enable */
#define HC_INTERRUPT_ALL			0x8000007FUL			/* All interrupts          */


/****************************/
/* HcRhDescriptorA Register */
/****************************/
#define PORT_POWER_SWITCHING			NO				/* Must be NO for ISP1161 */
#define OVER_CURRENT_PROTECTION			YES
#define PER_PORT_OVER_CURRENT_REPORT	NO
#define POWER_ON_TO_POWER_GOOD_TIME		50UL			/* Max. = 512 Msec. Use even number */

/* Bit field definition for register HcRhDescriptorA */
#define HC_RH_DESCRIPTORA_NDP		0x000000FFUL			/* Number of downstream ports  */
#define HC_RH_DESCRIPTORA_PSM		0x00000100UL			/* Power Switching Mode        */
#define HC_RH_DESCRIPTORA_NPS		0x00000200UL			/* No Power Switching          */
#define HC_RH_DESCRIPTORA_OCPM		0x00000800UL			/* OverCurrent Protection Mode */
#define HC_RH_DESCRIPTORA_NOCP		0x00001000UL			/* No OverCurrent Protection   */
#define HC_RH_DESCRIPTORA_POTPGT	0xFF000000UL			/* Power On To Power Good Time */

/****************************/
/* HcRhDescriptorB Register */
/****************************/
#define DEVICE_REMOVABLE			0x00000000UL
#define PORT_POWER_MASK				0x00000000UL

/* Bit field definition for register HcRhDescriptorB */
#define HC_RH_DESCRIPTORB_PPCM		0xFFFF0000UL			/* Port Power Control Mask     */
#define HC_RH_DESCRIPTORB_DR		0x0000FFFFUL			/* Device Removable            */


/* Bit field definition for register HcRhStatus */
#define HC_RH_STATUS_LPS			0x00000001UL			/* R: Local Power Status       */


/*---------------------------------------------------*/
/* Index of the ISP1161 HC extended 16-bit registers */
/*---------------------------------------------------*/
#define 	REG_HW_MODE						0x20			/* Hardware configuration register */
#define 	REG_DMA_CNFG					0x21			/* DMA configuration register      */
#define 	REG_XFER_CNTR					0x22			/* Transfer counter register       */
#define 	REG_IRQ							0x24			/* Interrupt register              */
#define 	REG_IRQ_MASK					0x25			/* Interrupt enable register       */
#define 	REG_CHIP_ID						0x27			/* Chip ID register                */
#define 	REG_SCRATCH						0x28			/* Scratch register                */
#define 	REG_RESET_DEV					0xA9			/* Reset register                  */
#define 	REG_ITL_BUFLEN					0x2A			/* ITL buffer length register      */
#define 	REG_ATL_BUFLEN					0x2B			/* ATL buffer length register      */
#define 	REG_BUFF_STS					0x2C			/* Buffer status register          */
#define 	REG_ITL0_LEN					0x2D			/* Read back ITL0 length register  */
#define 	REG_ITL1_LEN					0x2E			/* Read back ITL1 length register  */
#define 	REG_ITL_BUFF_IO					0x40			/* ITL buffer register             */
#define 	REG_ATL_BUFF_IO					0x41			/* ATL buffer register             */

#define 	PIC1_OCW1               		0x21
#define 	PIC1_CASCADE    				0xFB
#define 	PIC2_OCW1               		0xA1



/*------------------------------------------------------------------*/
/* ISP1161 external Interrupts configuration						*/
/*------------------------------------------------------------------*/

/**********************************/
/* HardwareConfiguration Register */
/**********************************/
#define 	GLOBAL_INT_PIN_ENABLE       	YES
#define 	INT_EDGE_TRIGGERED          	NO
#define 	INT_ACTIVE_HIGH             	YES

/****************************/
/* InterruptEnable Register */
/****************************/
#define 	SOF_INT_ENABLED             	YES
#define 	ATL_INT_ENABLED             	NO
#define 	EOT_INT_ENABLED             	NO
#define 	OPR_INT_ENABLED             	YES
#define 	HC_SUSPEND_INT_ENABLED      	NO
#define 	HC_RESUME_INT_ENABLED       	NO

/****************************/
/* HcFmInterval Register    */
/****************************/
#define		FRAME_INTERVAL					0x00002EDFUL
#define		FS_LARGEST_DATA					0x00002778UL

/*-----------------------------------------------*/
/* Bit field definition for REG_HW_MODE register */
/*-----------------------------------------------*/
#define 	INT_PIN_ENABLE					0X0001			/* Bit 0    */
#define 	INT_PIN_TRIGGER					0X0002			/* Bit 1    */
#define 	INT_OUTPUT_POLARITY				0X0004			/* Bit 2    */
#define 	DATA_BUS_WIDTH					0X0018			/* Bit 4..3 */

/*-------------------------------------------------------------*/
/* Bit field definition for REG_IRQ and REG_IRQ_MASK registers */
/*-------------------------------------------------------------*/
#define 	SOF_ITL_INT						0X0001			/* Bit 0: SOF and ITL interrupts */
#define 	ATL_INT							0X0002			/* Bit 1: ALT interrupt */
#define 	EOT_INT							0X0004			/* Bit 2: End of transfer interrupt */
#define 	OPR_INT							0X0010			/* Bit 4: HCOR int. */
#define 	HC_SUSPEND_INT					0X0020			/* Bit 5 */
#define 	HC_RESUME_INT					0X0040			/* Bit 6 */

/*-------------------------------------------------*/
/* Bit field definition for REG_BUFF_STS registers */
/*-------------------------------------------------*/
#define 	ISOA_BUFF_FULL					0X0001			/* Bit 0: ISOA buffer full */
#define 	ISOB_BUFF_FULL					0X0002			/* Bit 1: ISOB buffer full */
#define 	ATL_BUFF_FULL					0X0004			/* Bit 2: ATL buffer full */
#define 	ISOA_BUFF_DONE					0X0008			/* Bit 3: ISOA buffer done */
#define 	ISOB_BUFF_DONE					0X0010			/* Bit 4: ISOB buffer done */
#define 	ATL_BUFF_DONE					0X0020			/* Bit 5: ATL buffer done */



/*-----------------------------------------------------------*/
/* Definitions related to Philips Transfer Descriptors (PTD) */
/*-----------------------------------------------------------*/

/* Bit field definition for PTD byte 0 */
#define 	PTD_ACTUAL_BYTES70  			0XFF			/* Bit 7..0 */

/* Bit field definition for PTD byte 1 */
#define 	PTD_COMPLETION_CODE 			0XF0			/* Bit 7..4 */
#define 	PTD_ACTIVE      				0X08			/* Bit 3 */
#define 	PTD_TOGGLE      				0X04			/* Bit 2 */
#define 	PTD_ACTUAL_BYTES98  			0X03			/* Bit 1..0 */

/* Bit field definition for PTD byte 2 */
#define 	PTD_MAXPACKET70 				0XFF			/* Bit 7..0 */

/* Bit field definition for PTD byte 3 */
#define 	PTD_ED          				0XF0			/* Bit 7..4 */
#define 	PTD_LAST        				0X08			/* Bit 3 */
#define 	PTD_SPEED       				0X04			/* Bit 2 */
#define 	PTD_MAXPACKET98 				0X03 			/* Bit 1..0 */

/* Bit field definition for PTD byte 4 */
#define 	PTD_TOTAL70     				0XFF			/* Bit 7..0 */

/* Bit field definition for PTD byte 5 */
#define 	PTD_DIR         				0X0C			/* Bit 3..2 */
#define 	PTD_TOTAL98     				0X03			/* Bit 1..0 */

/* Bit field definition for PTD byte 6 */
#define 	PTD_FORMAT      				0X80			/* Bit 7 */
#define 	PTD_FUNCTION    				0X7F			/* Bit 6..0 */

extern void usb_claim_bandwidth (struct usb_device *dev, struct urb *urb,
		int bustime, int isoc);
extern void usb_release_bandwidth (struct usb_device *dev, struct urb *urb,
		int isoc);
extern int usb_check_bandwidth (struct usb_device *dev, struct urb *urb);