hcd_1161.h

isp116x系列USB芯片在LINUX下的驱动程序

	
/* roothub.a masks */
#define		RH_A_NDP					(0xff << 0)				/* number of downstream ports */
#define		RH_A_PSM					(1 << 8)				/* power switching mode */
#define		RH_A_NPS					(1 << 9)				/* no power switching */
#define		RH_A_DT						(1 << 10)				/* device type (mbz) */
#define		RH_A_OCPM					(1 << 11)				/* over current protection mode */
#define		RH_A_NOCP					(1 << 12)				/* no over current protection */
#define		RH_A_POTPGT					(0xff << 24)			/* power on to power good time */

#define 	min_hcd(a,b) 					(((a)<(b))?(a):(b))  
 

/* urb */
typedef struct 
{
	ed_t 				* ed;
	__u16 				length;									// number of tds associated with this request
	__u16 				td_cnt;									// number of tds already serviced
	int   				state;
	wait_queue_head_t 	* wait;
	td_t 				* td[0];								// list pointer to all corresponding TDs associated with this request

} urb_priv_t;

#define 	URB_DEL 					1

/*
 * This is the full ohci controller description
 *
 * Note how the "proper" USB information is just
 * a subset of what the full implementation needs. (Linus)
 */

typedef struct ohci {

	int 					disabled;							/* e.g. got a UE, we're hung */
	atomic_t 				resume_count;						/* defending against multiple resumes */

	struct list_head 		ohci_hcd_list;						/* list of all ohci_hcd */

	struct ohci 			* next; 							// chain of uhci device contexts
	// struct 				list_head urb_list; 				// list of all pending urbs
	// spinlock_t 			urb_list_lock; 						// lock to keep consistency 
  
	int 					ohci_int_load[32];					/* load of the 32 Interrupt Chains (for load balancing)*/
	ed_t 					* ed_rm_list[2];     				/* lists of all endpoints to be removed */
	ed_t 					* ed_bulktail;       				/* last endpoint of bulk list */
	ed_t 					* ed_controltail;    				/* last endpoint of control list */
 	ed_t 					* ed_isohead;        				/* first endpoint of iso list */
 	ed_t 					* ed_isotail;        				/* last endpoint of iso list */
	int 					in_isr;
	__u32 					hc_control;							/* copy of the hc control reg */
	struct usb_bus 			* bus;    
	struct usb_device 		* dev[128];							/* Usb devices attached to this HCD */
	struct virt_root_hub 	rh;									/* Virtual Root Hub information */

	/* Added for 1161 */
	void 					*p_atl_buffer;						/* Atl Buffer memory */
	void 					*p_itl_buffer;						/* Atl Buffer memory */
	unsigned int			irq;								/* Interrupt line for 1161 */
	
	__u32					uHcHcdControl_hcd;					/* Software Control Register of 1161 */
																/* Bit 5: Bulk List Enable (BLE) */
																/* Bit 4: Control List Enable (CLE) */
																/* Bit 3: Isochronous Enable (IE) */
																/* Bit 2: Periodic List Enable (PLE) */
																/* Bit 1..0: Control/Bulk Service Ratio */

	__u32					uHcHcdCommandStatus_hcd;			/* Software Command Status Register of 1161 */
																/* Bit 1: Control List Filled (CLF) */
																/* Bit 2: Bulk List Filled (BLF) */

	ed_t					* p_int_table[NUM_INTS];			/* Interrupt EndPoint Table (supposdly part of HCCA) */
	ed_t					* p_ed_bulkhead;					/* Bulk ED Head (supposdly part of OHCI register) */
	ed_t					* p_ed_controlhead;					/* Control ED Head (supposdly part of OHCI register) */
	ed_t					* p_ed_isohead;						/* Is this needed ??? */
	td_t					* pstDoneHead_hcd;					/* DoneHead */
	struct isotd_map_buffer		* pstIsoaPtdMapBuffer;				/* ISOA buffer td-ptd map buffer */
	struct isotd_map_buffer		* pstIsobPtdMapBuffer;				/* ISOB buffer td-ptd map buffer */
	


	/* PCI device handle and settings */
	struct pci_dev			*ohci_dev;
} ohci_t;


#define 	NUM_TDS						0				/* num of preallocated transfer descriptors */
#define 	NUM_EDS 					32				/* num of preallocated endpoint descriptors */

struct ohci_device {
	ed_t 				ed[NUM_EDS];
	int 				ed_cnt;
	wait_queue_head_t 	* wait;
};

// #define ohci_to_usb(ohci)			((ohci)->usb)
#define 	usb_to_ohci(usb)			((struct ohci_device *)(usb)->hcpriv)

/* hcd */
/* endpoint */
static int 	ep_link(ohci_t 	* ohci, ed_t 	* ed);
static int 	ep_unlink(ohci_t 	* ohci, ed_t 	* ed);
static ed_t * ep_add_ed(struct usb_device 	* usb_dev, unsigned int 	pipe, int 	interval, int 	load);
static void ep_rm_ed(struct usb_device 	* usb_dev, ed_t 	* ed);

/* td */
static void td_fill(unsigned int 	info, void 	* data, int 	len, struct urb 	* urb, int 	index);
static void td_submit_urb(struct urb 	* urb);

/* root hub */
static int rh_submit_urb(struct urb 	* urb);
static int rh_unlink_urb(struct urb 	* urb);
static int rh_init_int_timer(struct urb 	* urb);

/*-------------------------------------------------------------------------*/

#define 	ALLOC_FLAGS 					(in_interrupt () ? GFP_ATOMIC : GFP_KERNEL)
 
#ifdef PHCI_MEM_SLAB
#define		__alloc(t,c) 					kmem_cache_alloc(c,ALLOC_FLAGS)
#define		__free(c,x) 					kmem_cache_free(c,x)
static 		kmem_cache_t 					*td_cache, *ed_cache;

/*
 * WARNING:  do NOT use this with "forced slab debug"; it won't respect
 * our hardware alignment requirement.
 */
#ifndef PHCI_MEM_FLAGS
#define		PHCI_MEM_FLAGS 					0
#endif

static int ohci_1161_mem_init (void)
{
	/* redzoning (or forced debug!) breaks alignment */
	int	flags = (PHCI_MEM_FLAGS) & ~SLAB_RED_ZONE;

	/* TDs accessed by controllers and host */
	td_cache = kmem_cache_create ("ohci_td", sizeof (struct td), 0,
		flags | SLAB_HWCACHE_ALIGN, NULL, NULL);
	if (!td_cache) {
		dbg ("no TD cache?");
		return -ENOMEM;
	}

	/* EDs are accessed by controllers and host;  dev part is host-only */
	ed_cache = kmem_cache_create ("ohci_ed", sizeof (struct ohci_device), 0,
		flags | SLAB_HWCACHE_ALIGN, NULL, NULL);
	if (!ed_cache) {
		dbg ("no ED cache?");
		kmem_cache_destroy (td_cache);
		td_cache = 0;
		return -ENOMEM;
	}
	dbg ("slab flags 0x%x", flags);
	return 0;
}

static void ohci_1161_mem_cleanup (void)
{
	if (ed_cache && kmem_cache_destroy (ed_cache))
		err ("ed_cache remained");
	ed_cache = 0;

	if (td_cache && kmem_cache_destroy (td_cache))
		err ("td_cache remained");
	td_cache = 0;
}

#else
#define		__alloc(t,c) 					kmalloc(sizeof(t),ALLOC_FLAGS)
#define		__free(dev,x) 					kfree(x)
#define 	td_cache 						0
#define 	ed_cache 						0

static inline int ohci_1161_mem_init (void) { return 0; }
static inline void ohci_1161_mem_cleanup (void) { return; }


#endif /* PHCI_MEM_SLAB */


static inline struct td *
td_alloc (struct ohci *hc)
{
	struct td *td = (struct td *) __alloc (struct td, td_cache);
	return td;
}

static inline void
td_free (struct ohci *hc, struct td *td)
{
	__free (td_cache, td);
}


/* DEV + EDs ... only the EDs need to be consistent */
static inline struct ohci_device *
dev_alloc (struct ohci *hc)
{
	struct ohci_device *dev = (struct ohci_device *)
		__alloc (struct ohci_device, ed_cache);
	return dev;
}

static inline void
dev_free (struct ohci_device *dev)
{
	__free (ed_cache, dev);
}











/* Added ISP1161 related Constants */

#define 	YES						1
#define 	NO						0
#define 	ON						1
#define 	OFF						0
#define		MAX_GTD					64

/*----------------------------------------------------------*/
/*  ATL buffer processing definitions 						*/
/*----------------------------------------------------------*/
typedef struct td_tree_addr{
        __u32           uPipeHandle;
		__u32			pstHcdTd;						/* pointer to td is stored i.o index */
        __u32           uAtlNodeLength;
} td_tree_addr_t ;

typedef struct isotd_map_buffer{
		__u8			byStatus;						/* Status: filled (1) empty (0) */
		__u8			byActiveTds;					/* # of td's when filled */
		__u16			uByteCount;						/* Actual # of bytes of buffer filled */
		__u32			uFrameNumber;
		td_t			*pstIsoInDoneHead;	
		td_tree_addr_t	aItlTdTreeBridge[MAX_GTD];		/* PTD <-> TD mapping */
} isotd_map_buffer_t;




#define 	ATL_BUFF_LENGTH					2048UL					/* 2 KB */
#define 	ITL_BUFF_LENGTH					1024UL					/* 1 KB */
#define 	ATL_ALIGNMENT   				4						/* in bytes */
#define 	ITL_ALIGNMENT   				4						/* in bytes */
#define		INVALID_FRAME_NUMBER			0xFFFFFFFF				/* valid frame # is 0 - FFFF only */


/* Bit field definition for hwINFO of the td_t  */
#define 	HC_GTD_R						0x00040000UL			/* Buffer Rounding */
#define 	HC_GTD_DP						0x00180000UL			/* Direction/PID   */
#define 	HC_GTD_DI						0x00E00000UL			/* Delay Interrupt */
#define 	HC_GTD_T						0x03000000UL			/* Data Toggle     */
#define 	HC_GTD_MLSB						0x02000000UL			/* Data Toggle MSB */
#define 	HC_GTD_TLSB						0x01000000UL			/* Data Toggle LSB */
#define 	HC_GTD_EC						0x0C000000UL			/* Error Count     */
#define 	HC_GTD_CC						0xF0000000UL			/* Condition Code  */

/* Bit field definition for hwINFO of the ed_t */
#define 	HC_ED_FA						0x0000007FUL			/* Function Address */
#define 	HC_ED_EN						0x00000780UL			/* Endpoint Number */
#define 	HC_ED_DIR						0x00001800UL			/* Direction of data flow */
#define 	HC_ED_SPD						0x00002000UL			/* Device Speed */