📄 io430x42x.h
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unsigned short BLKWRT : 1; /* Enable bit for Flash segment write */
unsigned short KEY : 8; /* old definition */ /* Enable bit for Flash segment write */
} FCTL1_bit;
} @ 0x0128;
enum {
ERASE = 0x0002,
MERAS = 0x0004,
WRT = 0x0040,
BLKWRT = 0x0080,
};
__no_init volatile union
{
unsigned short FCTL2; /* FLASH Control 2 */
struct
{
unsigned short FN0 : 1; /* Devide Flash clock by 1 to 64 using FN0 to FN5 according to: */
unsigned short FN1 : 1; /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */
unsigned short FN2 : 1;
unsigned short FN3 : 1;
unsigned short FN4 : 1;
unsigned short FN5 : 1;
unsigned short SSEL0 : 1; /* Flash clock select 0 */
unsigned short SSEL1 : 1; /* Flash clock select 1 */
unsigned short KEY : 8;
} FCTL2_bit;
} @ 0x012A;
enum {
FN0 = 0x0001,
FN1 = 0x0002,
FN2 = 0x0004,
FN3 = 0x0008,
FN4 = 0x0010,
FN5 = 0x0020,
};
__no_init volatile union
{
unsigned short FCTL3; /* FLASH Control 3 */
struct
{
unsigned short BUSY : 1; /* Flash busy: 1 */
unsigned short KEYV : 1; /* Flash Key violation flag */
unsigned short ACCVIFG : 1; /* Flash Access violation flag */
unsigned short WAIT : 1; /* Wait flag for segment write */
unsigned short LOCK : 1; /* Lock bit: 1 - Flash is locked (read only) */
unsigned short EMEX : 1; /* Flash Emergency Exit */
unsigned short KEY : 8;
unsigned short : 2;
} FCTL3_bit;
} @ 0x012C;
enum {
BUSY = 0x0001,
KEYV = 0x0002,
ACCVIFG = 0x0004,
WAIT = 0x0008,
LOCK = 0x0010,
EMEX = 0x0020,
KEY = 0x2000,
};
#define FRKEY (0x9600) /* Flash key returned by read */
#define FWKEY (0xA500) /* Flash key for write */
#define FXKEY (0x3300) /* for use with XOR instruction */
#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */
#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */
#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */
#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */
/*-------------------------------------------------------------------------
* SD16
*-------------------------------------------------------------------------*/
__no_init volatile union
{
unsigned char SD16INCTL0; /* SD16 Input Control Register Channel 0 */
struct
{
unsigned char SD16INCH0 : 1; /* SD16 Input Channel select 0 */
unsigned char SD16INCH1 : 1; /* SD16 Input Channel select 1 */
unsigned char SD16INCH2 : 1; /* SD16 Input Channel select 2 */
unsigned char SD16GAIN0 : 1; /* AFE Input Pre-Amplifier Gain Select 0 */
unsigned char SD16GAIN1 : 1; /* AFE Input Pre-Amplifier Gain Select 1 */
unsigned char SD16GAIN2 : 1; /* AFE Input Pre-Amplifier Gain Select 2 */
unsigned char SD16INTDLY0 : 1; /* SD16 Interrupt Delay after 1.Conversion 0 */
unsigned char SD16INTDLY1 : 1; /* SD16 Interrupt Delay after 1.Conversion 1 */
} SD16INCTL0_bit;
} @ 0x00B0;
enum {
SD16INCH0 = 0x0001,
SD16INCH1 = 0x0002,
SD16INCH2 = 0x0004,
SD16GAIN0 = 0x0008,
SD16GAIN1 = 0x0010,
SD16GAIN2 = 0x0020,
SD16INTDLY0 = 0x0040,
SD16INTDLY1 = 0x0080,
};
__no_init volatile union
{
unsigned char SD16INCTL1; /* SD16 Input Control Register Channel 1 */
struct
{
unsigned char SD16INCH0 : 1; /* SD16 Input Channel select 0 */
unsigned char SD16INCH1 : 1; /* SD16 Input Channel select 1 */
unsigned char SD16INCH2 : 1; /* SD16 Input Channel select 2 */
unsigned char SD16GAIN0 : 1; /* AFE Input Pre-Amplifier Gain Select 0 */
unsigned char SD16GAIN1 : 1; /* AFE Input Pre-Amplifier Gain Select 1 */
unsigned char SD16GAIN2 : 1; /* AFE Input Pre-Amplifier Gain Select 2 */
unsigned char SD16INTDLY0 : 1; /* SD16 Interrupt Delay after 1.Conversion 0 */
unsigned char SD16INTDLY1 : 1; /* SD16 Interrupt Delay after 1.Conversion 1 */
} SD16INCTL1_bit;
} @ 0x00B1;
__no_init volatile union
{
unsigned char SD16INCTL2; /* SD16 Input Control Register Channel 2 */
struct
{
unsigned char SD16INCH0 : 1; /* SD16 Input Channel select 0 */
unsigned char SD16INCH1 : 1; /* SD16 Input Channel select 1 */
unsigned char SD16INCH2 : 1; /* SD16 Input Channel select 2 */
unsigned char SD16GAIN0 : 1; /* AFE Input Pre-Amplifier Gain Select 0 */
unsigned char SD16GAIN1 : 1; /* AFE Input Pre-Amplifier Gain Select 1 */
unsigned char SD16GAIN2 : 1; /* AFE Input Pre-Amplifier Gain Select 2 */
unsigned char SD16INTDLY0 : 1; /* SD16 Interrupt Delay after 1.Conversion 0 */
unsigned char SD16INTDLY1 : 1; /* SD16 Interrupt Delay after 1.Conversion 1 */
} SD16INCTL2_bit;
} @ 0x00B2;
/* SD16 Preload Register Channel 0 */
__no_init volatile unsigned char SD16PRE0 @ 0x00B8;
/* SD16 Preload Register Channel 1 */
__no_init volatile unsigned char SD16PRE1 @ 0x00B9;
/* SD16 Preload Register Channel 2 */
__no_init volatile unsigned char SD16PRE2 @ 0x00BA;
/* SD16 Internal Configuration Register 0 */
__no_init volatile unsigned char SD16CONF0 @ 0x00B7;
/* SD16 Internal Configuration Register 1 */
__no_init volatile unsigned char SD16CONF1 @ 0x00BF;
__no_init volatile union
{
unsigned short SD16CTL; /* Sigma Delta ADC 16 Control Register */
struct
{
unsigned short : 1;
unsigned short SD16OVIE : 1; /* Overflow Interupt Enable */
unsigned short SD16REFON : 1; /* Switch internal Reference on */
unsigned short SD16VMIDON : 1; /* Switch Vmid Buffer on */
unsigned short SD16SSEL0 : 1; /* SD16 Clock Source Select 0 */
unsigned short SD16SSEL1 : 1; /* SD16 Clock Source Select 1 */
unsigned short SD16DIV0 : 1; /* SD16 Clock Divider Select 0 */
unsigned short SD16DIV1 : 1; /* SD16 Clock Divider Select 1 */
unsigned short SD16LP : 1; /* SD16 Low Power Mode Enable */
} SD16CTL_bit;
} @ 0x0100;
enum {
SD16OVIE = 0x0002,
SD16REFON = 0x0004,
SD16VMIDON = 0x0008,
SD16SSEL0 = 0x0010,
SD16SSEL1 = 0x0020,
SD16DIV0 = 0x0040,
SD16DIV1 = 0x0080,
SD16LP = 0x0100,
};
__no_init volatile union
{
unsigned short SD16CCTL0; /* SD16 Channel 0 Control Register */
struct
{
unsigned short SD16GRP : 1; /* SD16 Grouping of Channels: 0:Off/1:On */
unsigned short SD16SC : 1; /* SD16 Start Conversion */
unsigned short SD16IFG : 1; /* SD16 Channel 0 Interrupt Flag */
unsigned short SD16IE : 1; /* SD16 Channel 0 Interrupt Enable */
unsigned short SD16DF : 1; /* SD16 Channel 0 Data Format: 0:Unipolar/1:Bipolar */
unsigned short SD16OVIFG : 1; /* SD16 Channel 0 Overflow Interrupt Flag */
unsigned short SD16LSBACC : 1; /* SD16 Channel 0 Access LSB of ADC */
unsigned short SD16LSBTOG : 1; /* SD16 Channel 0 Toggle LSB Output of ADC */
unsigned short SD16OSR0 : 1; /* SD16 Channel 0 OverSampling Ratio 0 */
unsigned short SD16OSR1 : 1; /* SD16 Channel 0 OverSampling Ratio 1 */
unsigned short SD16SNGL : 1; /* SD16 Channel 0 Single Conversion On/Off */
} SD16CCTL0_bit;
} @ 0x0102;
enum {
SD16GRP = 0x0001,
SD16SC = 0x0002,
SD16IFG = 0x0004,
SD16IE = 0x0008,
SD16DF = 0x0010,
SD16OVIFG = 0x0020,
SD16LSBACC = 0x0040,
SD16LSBTOG = 0x0080,
SD16OSR0 = 0x0100,
SD16OSR1 = 0x0200,
SD16SNGL = 0x0400,
};
__no_init volatile union
{
unsigned short SD16CCTL1; /* SD16 Channel 1 Control Register */
struct
{
unsigned short SD16GRP : 1; /* SD16 Grouping of Channels: 0:Off/1:On */
unsigned short SD16SC : 1; /* SD16 Start Conversion */
unsigned short SD16IFG : 1; /* SD16 Channel 1 Interrupt Flag */
unsigned short SD16IE : 1; /* SD16 Channel 1 Interrupt Enable */
unsigned short SD16DF : 1; /* SD16 Channel 1 Data Format: 0:Unipolar/1:Bipolar */
unsigned short SD16OVIFG : 1; /* SD16 Channel 1 Overflow Interrupt Flag */
unsigned short SD16LSBACC : 1; /* SD16 Channel 1 Access LSB of ADC */
unsigned short SD16LSBTOG : 1; /* SD16 Channel 1 Toggle LSB Output of ADC */
unsigned short SD16OSR0 : 1; /* SD16 Channel 1 OverSampling Ratio 0 */
unsigned short SD16OSR1 : 1; /* SD16 Channel 1 OverSampling Ratio 1 */
unsigned short SD16SNGL : 1; /* SD16 Channel 1 Single Conversion On/Off */
} SD16CCTL1_bit;
} @ 0x0104;
__no_init volatile union
{
unsigned short SD16CCTL2; /* SD16 Channel 2 Control Register */
struct
{
unsigned short SD16GRP : 1; /* SD16 Grouping of Channels: 0:Off/1:On */
unsigned short SD16SC : 1; /* SD16 Start Conversion */
unsigned short SD16IFG : 1; /* SD16 Channel 2 Interrupt Flag */
unsigned short SD16IE : 1; /* SD16 Channel 2 Interrupt Enable */
unsigned short SD16DF : 1; /* SD16 Channel 2 Data Format: 0:Unipolar/1:Bipolar */
unsigned short SD16OVIFG : 1; /* SD16 Channel 2 Overflow Interrupt Flag */
unsigned short SD16LSBACC : 1; /* SD16 Channel 2 Access LSB of ADC */
unsigned short SD16LSBTOG : 1; /* SD16 Channel 2 Toggle LSB Output of ADC */
unsigned short SD16OSR0 : 1; /* SD16 Channel 2 OverSampling Ratio 0 */
unsigned short SD16OSR1 : 1; /* SD16 Channel 2 OverSampling Ratio 1 */
unsigned short SD16SNGL : 1; /* SD16 Channel 2 Single Conversion On/Off */
} SD16CCTL2_bit;
} @ 0x0106;
/* SD16 Interrupt Vector Register */
__no_init volatile unsigned short SD16IV @ 0x0110;
/* SD16 Channel 0 Conversion Memory */
__no_init volatile unsigned short SD16MEM0 @ 0x0112;
/* SD16 Channel 1 Conversion Memory */
__no_init volatile unsigned short SD16MEM1 @ 0x0114;
/* SD16 Channel 2 Conversion Memory */
__no_init volatile unsigned short SD16MEM2 @ 0x0116;
#define SD16GAIN_1 (0x0000) /* AFE Input Pre-Amplifier Gain Select *1 */
#define SD16GAIN_2 (0x0008) /* AFE Input Pre-Amplifier Gain Select *2 */
#define SD16GAIN_4 (0x0010) /* AFE Input Pre-Amplifier Gain Select *4 */
#define SD16GAIN_8 (0x0018) /* AFE Input Pre-Amplifier Gain Select *8 */
#define SD16GAIN_16 (0x0020) /* AFE Input Pre-Amplifier Gain Select *16 */
#define SD16GAIN_32 (0x0028) /* AFE Input Pre-Amplifier Gain Select *32 */
#define SD16INCH_0 (0x0000) /* SD16 Input Channel select input */
#define SD16INCH_1 (0x0001) /* SD16 Input Channel select input */
#define SD16INCH_2 (0x0002) /* SD16 Input Channel select input */
#define SD16INCH_3 (0x0003) /* SD16 Input Channel select input */
#define SD16INCH_4 (0x0004) /* SD16 Input Channel select input */
#define SD16INCH_5 (0x0005) /* SD16 Input Channel select input */
#define SD16INCH_6 (0x0006) /* SD16 Input Channel select Temp */
#define SD16INCH_7 (0x0007) /* SD16 Input Channel select Offset */
#define SD16DIV_0 (0x0000) /* SD16 Clock Divider Select /1 */
#define SD16DIV_1 (SD16DIV0) /* SD16 Clock Divider Select /2 */
#define SD16DIV_2 (SD16DIV1) /* SD16 Clock Divider Select /4 */
#define SD16DIV_3 (SD16DIV0+SD16DIV1) /* SD16 Clock Divider Select /8 */
#define SD16SSEL_0 (0x0000) /* SD16 Clock Source Select MCLK */
#define SD16SSEL_1 (SD16SSEL0) /* SD16 Clock Source Select SMCLK */
#define SD16SSEL_2 (SD16SSEL1) /* SD16 Clock Source Select ACLK */
#define SD16SSEL_3 (SD16SSEL0+SD16SSEL1) /* SD16 Clock Source Select TACLK */
#define SD16OSR_256 (0x0000) /* SD16 Channel x OverSampling Ratio 256 */
#define SD16OSR_128 (0x0100) /* SD16 Channel x OverSampling Ratio 128 */
#define SD16OSR_64 (0x0200) /* SD16 Channel x OverSampling Ratio 64 */
#define SD16OSR_32 (0x0300) /* SD16 Channel x OverSampling Ratio 32 */
#pragma language=default
#endif /* __IAR_SYSTEMS_ICC__ */
/************************************************************
* Timer A interrupt vector value
************************************************************/
#define TAIV_CCIFG1 (2) /* Capture/compare 1 */
#define TAIV_CCIFG2 (4) /* Capture/compare 2 */
#define TAIV_CCIFG3 (6) /* Capture/compare 3 */
#define TAIV_CCIFG4 (8) /* Capture/compare 4 */
#define TAIV_TAIFG (10) /* Timer overflow */
/************************************************************
* Interrupt Vectors (offset from 0xFFE0)
************************************************************/
#define BASICTIMER_VECTOR (0 * 2u) /* 0xFFE0 Basic Timer */
#define PORT2_VECTOR (1 * 2u) /* 0xFFE2 Port 2 */
#define PORT1_VECTOR (4 * 2u) /* 0xFFE8 Port 1 */
#define TIMERA1_VECTOR (5 * 2u) /* 0xFFEA Timer A CC1-2, TA */
#define TIMERA0_VECTOR (6 * 2u) /* 0xFFEC Timer A CC0 */
#define USART0TX_VECTOR (8 * 2u) /* 0xFFF0 USART 0 Transmit */
#define USART0RX_VECTOR (9 * 2u) /* 0xFFF2 USART 0 Receive */
#define WDT_VECTOR (10 * 2u) /* 0xFFF4 Watchdog Timer */
#define SD16_VECTOR (12 * 2u) /* 0xFFF8 Sigma Delta ADC */
#define NMI_VECTOR (14 * 2u) /* 0xFFFC Non-maskable */
#define RESET_VECTOR (15 * 2u) /* 0xFFFE Reset [Highest Priority] */
#define UART0TX_VECTOR USART0TX_VECTOR
#define UART0RX_VECTOR USART0RX_VECTOR
#endif /* __IO430xxxx */
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