📄 io430x42x.h
字号:
#define LCDOG2_7 (LCDP0) /* S0 - S15 see Datasheet */
#define LCDOG3_7 (LCDP1) /* S0 - S19 see Datasheet */
#define LCDOG4_7 (LCDP1+LCDP0) /* S0 - S23 see Datasheet */
#define LCDOG5_7 (LCDP2) /* S0 - S27 see Datasheet */
#define LCDOG6_7 (LCDP2+LCDP0) /* S0 - S31 see Datasheet */
#define LCDOG7 (LCDP2+LCDP1) /* S0 - S35 see Datasheet */
#define LCDOGOFF (LCDP2+LCDP1+LCDP0) /* S0 - S39 see Datasheet */
#define LCDMA (LCDM10) /* LCD Memory A */
#define LCDMB (LCDM11) /* LCD Memory B */
#define LCDMC (LCDM12) /* LCD Memory C */
#define LCDMD (LCDM13) /* LCD Memory D */
#define LCDME (LCDM14) /* LCD Memory E */
#define LCDMF (LCDM15) /* LCD Memory F */
/*-------------------------------------------------------------------------
* USART 0
*-------------------------------------------------------------------------*/
__no_init volatile union
{
unsigned char U0CTL; /* USART 0 Control */
struct
{
unsigned char SWRST : 1; /* USART Software Reset */
unsigned char MM : 1; /* Master Mode off/on */
unsigned char SYNC : 1; /* UART / SPI mode */
unsigned char LISTEN : 1; /* Listen mode */
unsigned char CHAR : 1; /* Data 0:7-bits / 1:8-bits */
unsigned char SPB : 1; /* Stop Bits 0:one / 1: two */
unsigned char PEV : 1; /* Parity 0:odd / 1:even */
unsigned char PENA : 1; /* Parity enable */
} U0CTL_bit;
} @ 0x0070;
enum {
SWRST = 0x0001,
MM = 0x0002,
SYNC = 0x0004,
LISTEN = 0x0008,
CHAR = 0x0010,
SPB = 0x0020,
PEV = 0x0040,
PENA = 0x0080,
};
__no_init volatile union
{
unsigned char U0TCTL; /* USART 0 Transmit Control */
struct
{
unsigned char TXEPT : 1; /* TX Buffer empty */
unsigned char STC : 1; /* SPI: STC enable 0:on / 1:off */
unsigned char TXWAKE : 1; /* TX Wake up mode */
unsigned char URXSE : 1; /* Receive Start edge select */
unsigned char SSEL0 : 1; /* Clock Source Select 0 */
unsigned char SSEL1 : 1; /* Clock Source Select 1 */
unsigned char CKPL : 1; /* Clock Polarity */
unsigned char CKPH : 1; /* SPI: Clock Phase */
} U0TCTL_bit;
} @ 0x0071;
enum {
TXEPT = 0x0001,
STC = 0x0002,
TXWAKE = 0x0004,
URXSE = 0x0008,
SSEL0 = 0x0010,
SSEL1 = 0x0020,
CKPL = 0x0040,
CKPH = 0x0080,
};
__no_init volatile union
{
unsigned char U0RCTL; /* USART 0 Receive Control */
struct
{
unsigned char RXERR : 1; /* RX Error Error */
unsigned char RXWAKE : 1; /* RX Wake up detect */
unsigned char URXWIE : 1; /* RX Wake up interrupt enable */
unsigned char URXEIE : 1; /* RX Error interrupt enable */
unsigned char BRK : 1; /* Break detected */
unsigned char OE : 1; /* Overrun Error */
unsigned char PE : 1; /* Parity Error */
unsigned char FE : 1; /* Frame Error */
} U0RCTL_bit;
} @ 0x0072;
enum {
RXERR = 0x0001,
RXWAKE = 0x0002,
URXWIE = 0x0004,
URXEIE = 0x0008,
BRK = 0x0010,
OE = 0x0020,
PE = 0x0040,
FE = 0x0080,
};
/* USART 0 Modulation Control */
__no_init volatile unsigned char U0MCTL @ 0x0073;
/* USART 0 Baud Rate 0 */
__no_init volatile unsigned char U0BR0 @ 0x0074;
/* USART 0 Baud Rate 1 */
__no_init volatile unsigned char U0BR1 @ 0x0075;
/* USART 0 Receive Buffer */
__no_init volatile unsigned __READ char U0RXBUF @ 0x0076;
/* USART 0 Transmit Buffer */
__no_init volatile unsigned char U0TXBUF @ 0x0077;
/* Alternate register names */
#define UCTL0 U0CTL /* USART 0 Control */
#define UTCTL0 U0TCTL /* USART 0 Transmit Control */
#define URCTL0 U0RCTL /* USART 0 Receive Control */
#define UMCTL0 U0MCTL /* USART 0 Modulation Control */
#define UBR00 U0BR0 /* USART 0 Baud Rate 0 */
#define UBR10 U0BR1 /* USART 0 Baud Rate 1 */
#define RXBUF0 U0RXBUF /* USART 0 Receive Buffer */
#define TXBUF0 U0TXBUF /* USART 0 Transmit Buffer */
#define UCTL0_ U0CTL /* USART 0 Control */
#define UTCTL0_ U0TCTL /* USART 0 Transmit Control */
#define URCTL0_ U0RCTL /* USART 0 Receive Control */
#define UMCTL0_ U0MCTL /* USART 0 Modulation Control */
#define UBR00_ U0BR0 /* USART 0 Baud Rate 0 */
#define UBR10_ U0BR1 /* USART 0 Baud Rate 1 */
#define RXBUF0_ U0RXBUF /* USART 0 Receive Buffer */
#define TXBUF0_ U0TXBUF /* USART 0 Transmit Buffer */
#define UCTL_0 U0CTL /* USART 0 Control */
#define UTCTL_0 U0TCTL /* USART 0 Transmit Control */
#define URCTL_0 U0RCTL /* USART 0 Receive Control */
#define UMCTL_0 U0MCTL /* USART 0 Modulation Control */
#define UBR0_0 U0BR0 /* USART 0 Baud Rate 0 */
#define UBR1_0 U0BR1 /* USART 0 Baud Rate 1 */
#define RXBUF_0 U0RXBUF /* USART 0 Receive Buffer */
#define TXBUF_0 U0TXBUF /* USART 0 Transmit Buffer */
#define UCTL_0_ U0CTL /* USART 0 Control */
#define UTCTL_0_ U0TCTL /* USART 0 Transmit Control */
#define URCTL_0_ U0RCTL /* USART 0 Receive Control */
#define UMCTL_0_ U0MCTL /* USART 0 Modulation Control */
#define UBR0_0_ U0BR0 /* USART 0 Baud Rate 0 */
#define UBR1_0_ U0BR1 /* USART 0 Baud Rate 1 */
#define RXBUF_0_ U0RXBUF /* USART 0 Receive Buffer */
#define TXBUF_0_ U0TXBUF /* USART 0 Transmit Buffer */
/*-------------------------------------------------------------------------
* Timer A
*-------------------------------------------------------------------------*/
__no_init volatile union
{
unsigned __READ short TAIV; /* Timer A Interrupt Vector Word */
struct
{
unsigned __READ short : 1;
unsigned __READ short IRQVEC : 3;
unsigned __READ short : 12;
} TAIV_bit;
} @ 0x012E;
enum {
IRQVEC = 0x0008,
};
__no_init volatile union
{
unsigned short TACTL; /* Timer A Control */
struct
{
unsigned short TAIFG : 1; /* Timer A counter interrupt flag */
unsigned short TAIE : 1; /* Timer A counter interrupt enable */
unsigned short TACLR : 1; /* Timer A counter clear */
unsigned short : 1;
unsigned short TAMC : 2; /* Timer A mode control 0 */
unsigned short TAID : 2; /* Timer A clock input devider */
unsigned short TASSEL : 2; /* Timer A clock source select */
unsigned short : 6;
} TACTL_bit;
} @ 0x0160;
enum {
TAIFG = 0x0001,
TAIE = 0x0002,
TACLR = 0x0004,
TAMC = 0x0020,
TAID = 0x0080,
TASSEL = 0x0200,
};
__no_init volatile union
{
unsigned short TACCTL0; /* Timer A Capture/Compare Control 0 */
struct
{
unsigned short CCIFG : 1; /* Capture/compare interrupt flag */
unsigned short COV : 1; /* Capture/compare overflow flag */
unsigned short OUT : 1; /* PWM Output signal if output mode 0 */
unsigned short CCI : 1; /* Capture input signal (read) */
unsigned short CCIE : 1; /* Capture/compare interrupt enable */
unsigned short OUTMOD : 3; /* Output mode */
unsigned short CAP : 1; /* Capture mode: 1 /Compare mode : 0 */
unsigned short : 1;
unsigned short SCCI : 1; /* Latched capture signal (read) */
unsigned short SCS : 1; /* Capture sychronize */
unsigned short CCIS : 2; /* Capture input select */
unsigned short CM : 2; /* Capture mode */
} TACCTL0_bit;
} @ 0x0162;
enum {
CCIFG = 0x0001,
COV = 0x0002,
OUT = 0x0004,
CCI = 0x0008,
CCIE = 0x0010,
OUTMOD = 0x0080,
CAP = 0x0100,
SCCI = 0x0400,
SCS = 0x0800,
CCIS = 0x2000,
CM = 0x8000,
};
__no_init volatile union
{
unsigned short TACCTL1; /* Timer A Capture/Compare Control 1 */
struct
{
unsigned short CCIFG : 1; /* Capture/compare interrupt flag */
unsigned short COV : 1; /* Capture/compare overflow flag */
unsigned short OUT : 1; /* PWM Output signal if output mode 0 */
unsigned short CCI : 1; /* Capture input signal (read) */
unsigned short CCIE : 1; /* Capture/compare interrupt enable */
unsigned short OUTMOD : 3; /* Output mode */
unsigned short CAP : 1; /* Capture mode: 1 /Compare mode : 0 */
unsigned short : 1;
unsigned short SCCI : 1; /* Latched capture signal (read) */
unsigned short SCS : 1; /* Capture sychronize */
unsigned short CCIS : 2; /* Capture input select */
unsigned short CM : 2; /* Capture mode */
} TACCTL1_bit;
} @ 0x0164;
__no_init volatile union
{
unsigned short TACCTL2; /* Timer A Capture/Compare Control 2 */
struct
{
unsigned short CCIFG : 1; /* Capture/compare interrupt flag */
unsigned short COV : 1; /* Capture/compare overflow flag */
unsigned short OUT : 1; /* PWM Output signal if output mode 0 */
unsigned short CCI : 1; /* Capture input signal (read) */
unsigned short CCIE : 1; /* Capture/compare interrupt enable */
unsigned short OUTMOD : 3; /* Output mode */
unsigned short CAP : 1; /* Capture mode: 1 /Compare mode : 0 */
unsigned short : 1;
unsigned short SCCI : 1; /* Latched capture signal (read) */
unsigned short SCS : 1; /* Capture sychronize */
unsigned short CCIS : 2; /* Capture input select */
unsigned short CM : 2; /* Capture mode */
} TACCTL2_bit;
} @ 0x0166;
/* Timer A */
__no_init volatile unsigned short TAR @ 0x0170;
/* Timer A Capture/Compare 0 */
__no_init volatile unsigned short TACCR0 @ 0x0172;
/* Timer A Capture/Compare 1 */
__no_init volatile unsigned short TACCR1 @ 0x0174;
/* Timer A Capture/Compare 2 */
__no_init volatile unsigned short TACCR2 @ 0x0176;
#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */
#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */
#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */
#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */
#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */
#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */
#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */
#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */
#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */
#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */
#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */
#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */
#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */
#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */
#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
/* Alternate register names */
#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */
#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */
#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */
#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */
#define CCTL0_ TACCTL0 /* Timer A Capture/Compare Control 0 */
#define CCTL1_ TACCTL1 /* Timer A Capture/Compare Control 1 */
#define CCTL2_ TACCTL2 /* Timer A Capture/Compare Control 2 */
#define CCR0_ TACCR0 /* Timer A Capture/Compare 0 */
#define CCR1_ TACCR1 /* Timer A Capture/Compare 1 */
#define CCR2_ TACCR2 /* Timer A Capture/Compare 2 */
/*-------------------------------------------------------------------------
* Flash Memory
*-------------------------------------------------------------------------*/
__no_init volatile union
{
unsigned short FCTL1; /* FLASH Control 1 */
struct
{
unsigned short : 1;
unsigned short ERASE : 1; /* Enable bit for Flash segment erase */
unsigned short MERAS : 1; /* Enable bit for Flash mass erase */
unsigned short : 3;
unsigned short WRT : 1; /* Enable bit for Flash write */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -