📄 io430x42x.h
字号:
unsigned char BTSSEL : 1; /* fBT = fMCLK (main clock) */
} BTCTL_bit;
} @ 0x0040;
enum {
BTIP = 0x0004,
BTFRFQ = 0x0010,
BTDIV = 0x0020,
BTHOLD = 0x0040,
BTSSEL = 0x0080,
};
/* Basic Timer Count 1 */
__no_init volatile unsigned char BTCNT1 @ 0x0046;
/* Basic Timer Count 2 */
__no_init volatile unsigned char BTCNT2 @ 0x0047;
/* Frequency of the BTCNT2 coded with Bit 5 and 7 in BTCTL */
#define BT_fCLK2_ACLK (0x00)
#define BT_fCLK2_ACLK_DIV256 (BTDIV)
#define BT_fCLK2_MCLK (BTSSEL)
/* Interrupt interval time fINT coded with Bits 0-2 in BTCTL */
#define BT_fCLK2_DIV2 (0x00) /* fINT = fCLK2:2 (default) */
#define BT_fCLK2_DIV4 (BTIP0) /* fINT = fCLK2:4 */
#define BT_fCLK2_DIV8 (BTIP1) /* fINT = fCLK2:8 */
#define BT_fCLK2_DIV16 (BTIP1+BTIP0) /* fINT = fCLK2:16 */
#define BT_fCLK2_DIV32 (BTIP2) /* fINT = fCLK2:32 */
#define BT_fCLK2_DIV64 (BTIP2+BTIP0) /* fINT = fCLK2:64 */
#define BT_fCLK2_DIV128 (BTIP2+BTIP1) /* fINT = fCLK2:128 */
#define BT_fCLK2_DIV256 (BTIP2+BTIP1+BTIP0) /* fINT = fCLK2:256 */
/* Frequency of LCD coded with Bits 3-4 */
#define BT_fLCD_DIV32 (0x00) /* fLCD = fACLK:32 (default) */
#define BT_fLCD_DIV64 (BTFRFQ0) /* fLCD = fACLK:64 */
#define BT_fLCD_DIV128 (BTFRFQ1) /* fLCD = fACLK:128 */
#define BT_fLCD_DIV256 (BTFRFQ1+BTFRFQ0) /* fLCD = fACLK:256 */
/* LCD frequency values with fBT=fACLK */
#define BT_fLCD_1K (0x00) /* fACLK:32 (default) */
#define BT_fLCD_512 (BTFRFQ0) /* fACLK:64 */
#define BT_fLCD_256 (BTFRFQ1) /* fACLK:128 */
#define BT_fLCD_128 (BTFRFQ1+BTFRFQ0) /* fACLK:256 */
/* LCD frequency values with fBT=fMCLK */
#define BT_fLCD_31K (BTSSEL) /* fMCLK:32 */
#define BT_fLCD_15_5K (BTSSEL+BTFRFQ0) /* fMCLK:64 */
#define BT_fLCD_7_8K (BTSSEL+BTFRFQ1+BTFRFQ0) /* fMCLK:256 */
/* with assumed vlues of fACLK=32KHz, fMCLK=1MHz */
/* fBT=fACLK is thought for longer interval times */
#define BT_ADLY_0_064 (0x00) /* 0.064ms interval (default) */
#define BT_ADLY_0_125 (BTIP0) /* 0.125ms */
#define BT_ADLY_0_25 (BTIP1) /* 0.25ms */
#define BT_ADLY_0_5 (BTIP1+BTIP0) /* 0.5ms */
#define BT_ADLY_1 (BTIP2) /* 1ms */
#define BT_ADLY_2 (BTIP2+BTIP0) /* 2ms */
#define BT_ADLY_4 (BTIP2+BTIP1) /* 4ms */
#define BT_ADLY_8 (BTIP2+BTIP1+BTIP0) /* 8ms */
#define BT_ADLY_16 (BTDIV) /* 16ms */
#define BT_ADLY_32 (BTDIV+BTIP0) /* 32ms */
#define BT_ADLY_64 (BTDIV+BTIP1) /* 64ms */
#define BT_ADLY_125 (BTDIV+BTIP1+BTIP0) /* 125ms */
#define BT_ADLY_250 (BTDIV+BTIP2) /* 250ms */
#define BT_ADLY_500 (BTDIV+BTIP2+BTIP0) /* 500ms */
#define BT_ADLY_1000 (BTDIV+BTIP2+BTIP1) /* 1000ms */
#define BT_ADLY_2000 (BTDIV+BTIP2+BTIP1+BTIP0) /* 2000ms */
/* fCLK2=fMCLK (1MHz) is thought for short interval times */
/* the timing for short intervals is more precise than ACLK */
/* NOTE */
/* Be sure that the SCFQCTL-Register is set to 01Fh so that fMCLK=1MHz */
/* Too low interval time results in interrupts too frequent for the processor to handle! */
#define BT_MDLY_0_002 (BTSSEL) /* 0.002ms interval *** interval times */
#define BT_MDLY_0_004 (BTSSEL+BTIP0) /* 0.004ms *** too short for */
#define BT_MDLY_0_008 (BTSSEL+BTIP1) /* 0.008ms *** interrupt */
#define BT_MDLY_0_016 (BTSSEL+BTIP1+BTIP0) /* 0.016ms *** handling */
#define BT_MDLY_0_032 (BTSSEL+BTIP2) /* 0.032ms */
#define BT_MDLY_0_064 (BTSSEL+BTIP2+BTIP0) /* 0.064ms */
#define BT_MDLY_0_125 (BTSSEL+BTIP2+BTIP1) /* 0.125ms */
#define BT_MDLY_0_25 (BTSSEL+BTIP2+BTIP1+BTIP0)/* 0.25ms */
/* Reset/Hold coded with Bits 6-7 in BT(1)CTL */
/* this is for BT */
#define BTRESET_CNT1 (BTRESET) /* BTCNT1 is reset while BTRESET is set */
#define BTRESET_CNT1_2 (BTRESET+BTDIV) /* BTCNT1 .AND. BTCNT2 are reset while ~ is set */
/* this is for BT1 */
#define BTHOLD_CNT1 (BTHOLD) /* BTCNT1 is held while BTHOLD is set */
#define BTHOLD_CNT1_2 (BTHOLD+BTDIV) /* BT1CNT1 .AND. BT1CNT2 are held while ~ is set */
/* INTERRUPT CONTROL BITS */
/* #define BTIE 0x80 */
/* #define BTIFG 0x80 */
/*-------------------------------------------------------------------------
* System Clock, FFL+ (x41x)
*-------------------------------------------------------------------------*/
__no_init volatile union
{
unsigned char SCFI0; /* System Clock Frequency Integrator 0 */
struct
{
unsigned char : 2;
unsigned char FN_2 : 1; /* fDCOCLK = 1.4-12MHz */
unsigned char FN_3 : 1; /* fDCOCLK = 2.2-17Mhz */
unsigned char FN_4 : 1; /* fDCOCLK = 3.2-25Mhz */
unsigned char FN_8 : 1; /* fDCOCLK = 5-40Mhz */
unsigned char FLLD : 2; /* Loop Divider */
} SCFI0_bit;
} @ 0x0050;
enum {
FN_2 = 0x0004,
FN_3 = 0x0008,
FN_4 = 0x0010,
FN_8 = 0x0020,
FLLD = 0x0080,
};
/* System Clock Frequency Integrator 1 */
__no_init volatile unsigned char SCFI1 @ 0x0051;
/* System Clock Frequency Control */
__no_init volatile unsigned char SCFQCTL @ 0x0052;
__no_init volatile union
{
unsigned char FLL_CTL0; /* FLL+ Control 0 */
struct
{
unsigned char DCOF : 1; /* DCO Fault Flag */
unsigned char LFOF : 1; /* Low Frequency Oscillator Fault Flag */
unsigned char XT1OF : 1; /* High Frequency Oscillator Fault Flag */
unsigned char : 1;
unsigned char OSCCAP0 : 1; /* XIN/XOUT Cap 0 */
unsigned char OSCCAP1 : 1; /* XIN/XOUT Cap 1 */
unsigned char XTS_FLL : 1; /* 1: Selects high-freq. oscillator */
unsigned char DCOPLUS : 1; /* DCO+ Enable */
} FLL_CTL0_bit;
} @ 0x0053;
enum {
DCOF = 0x0001,
LFOF = 0x0002,
XT1OF = 0x0004,
OSCCAP0 = 0x0010,
OSCCAP1 = 0x0020,
XTS_FLL = 0x0040,
DCOPLUS = 0x0080,
};
__no_init volatile union
{
unsigned char FLL_CTL1; /* FLL+ Control 1 */
struct
{
unsigned char FLL_DIV0 : 1; /* FLL+ Divide Px.x/ACLK 0 */
unsigned char FLL_DIV1 : 1; /* FLL+ Divide Px.x/ACLK 1 */
} FLL_CTL1_bit;
} @ 0x0054;
enum {
FLL_DIV0 = 0x0001,
FLL_DIV1 = 0x0002,
};
#define FLLD_1 (0x00) /* Multiply Selected Loop Freq. By 1 */
#define FLLD_2 (0x40) /* Multiply Selected Loop Freq. By 2 */
#define FLLD_4 (0x80) /* Multiply Selected Loop Freq. By 4 */
#define FLLD_8 (0xC0) /* Multiply Selected Loop Freq. By 8 */
/* System clock frequency values fMCLK coded with Bits 0-6 in SCFQCTL */
/* #define SCFQ_32K 0x00 fMCLK=1*fACLK only a range from */
#define SCFQ_64K (0x01) /* fMCLK=2*fACLK 1+1 to 127+1 is possible */
#define SCFQ_128K (0x03) /* fMCLK=4*fACLK */
#define SCFQ_256K (0x07) /* fMCLK=8*fACLK */
#define SCFQ_512K (0x0F) /* fMCLK=16*fACLK */
#define SCFQ_1M (0x1F) /* fMCLK=32*fACLK */
#define SCFQ_2M (0x3F) /* fMCLK=64*fACLK */
#define SCFQ_4M (0x7F) /* fMCLK=128*fACLK */
#define SCFQ_M (0x80) /* Modulation Disable */
#define XCAP0PF (0x00) /* XIN Cap = XOUT Cap = 0pf */
#define XCAP10PF (0x10) /* XIN Cap = XOUT Cap = 10pf */
#define XCAP14PF (0x20) /* XIN Cap = XOUT Cap = 14pf */
#define XCAP18PF (0x30) /* XIN Cap = XOUT Cap = 18pf */
#define OSCCAP_0 (0x00) /* XIN Cap = XOUT Cap = 0pf */
#define OSCCAP_1 (0x10) /* XIN Cap = XOUT Cap = 10pf */
#define OSCCAP_2 (0x20) /* XIN Cap = XOUT Cap = 14pf */
#define OSCCAP_3 (0x30) /* XIN Cap = XOUT Cap = 18pf */
#define FLL_DIV_1 (0x00) /* FLL+ Divide Px.x/ACLK By 1 */
#define FLL_DIV_2 (0x01) /* FLL+ Divide Px.x/ACLK By 2 */
#define FLL_DIV_4 (0x02) /* FLL+ Divide Px.x/ACLK By 4 */
#define FLL_DIV_8 (0x03) /* FLL+ Divide Px.x/ACLK By 8 */
/* INTERRUPT CONTROL BITS */
/* These two bits are defined in the Special Function Registers */
/* #define OFIFG 0x02 */
/* #define OFIE 0x02 */
/*-------------------------------------------------------------------------
* Brown-Out, Supply Voltage Supervision (SVS)
*-------------------------------------------------------------------------*/
__no_init volatile union
{
unsigned char SVSCTL; /* SVS Control */
struct
{
unsigned char SVSFG : 1; /* SVS Flag */
unsigned char SVSOP : 1; /* SVS output (read only) */
unsigned char SVSON : 1; /* Switches the SVS on/off */
unsigned char PORON : 1; /* Enable POR Generation if Low Voltage */
unsigned char VLD : 4;
} SVSCTL_bit;
} @ 0x0056;
enum {
SVSFG = 0x0001,
SVSOP = 0x0002,
SVSON = 0x0004,
PORON = 0x0008,
VLD = 0x0080,
};
#define VLDOFF (0x00)
#define VLD_1_8V (0x10)
/*-------------------------------------------------------------------------
* LCD Register
*-------------------------------------------------------------------------*/
__no_init volatile union
{
unsigned char LCDCTL; /* LCD Control */
struct
{
unsigned char LCDON : 1;
unsigned char : 1;
unsigned char LCDSON : 1;
unsigned char LCDMX0 : 1;
unsigned char LCDMX1 : 1;
unsigned char LCDP0 : 1;
unsigned char LCDP1 : 1;
unsigned char LCDP2 : 1;
} LCDCTL_bit;
} @ 0x0090;
enum {
LCDON = 0x0001,
LCDSON = 0x0004,
LCDMX0 = 0x0008,
LCDMX1 = 0x0010,
LCDP0 = 0x0020,
LCDP1 = 0x0040,
LCDP2 = 0x0080,
};
/* LCD Memory 1 */
__no_init volatile unsigned char LCDM1 @ 0x0091;
/* LCD Memory 2 */
__no_init volatile unsigned char LCDM2 @ 0x0092;
/* LCD Memory 3 */
__no_init volatile unsigned char LCDM3 @ 0x0093;
/* LCD Memory 4 */
__no_init volatile unsigned char LCDM4 @ 0x0094;
/* LCD Memory 5 */
__no_init volatile unsigned char LCDM5 @ 0x0095;
/* LCD Memory 6 */
__no_init volatile unsigned char LCDM6 @ 0x0096;
/* LCD Memory 7 */
__no_init volatile unsigned char LCDM7 @ 0x0097;
/* LCD Memory 8 */
__no_init volatile unsigned char LCDM8 @ 0x0098;
/* LCD Memory 9 */
__no_init volatile unsigned char LCDM9 @ 0x0099;
/* LCD Memory 10 */
__no_init volatile unsigned char LCDM10 @ 0x009A;
/* LCD Memory 11 */
__no_init volatile unsigned char LCDM11 @ 0x009B;
/* LCD Memory 12 */
__no_init volatile unsigned char LCDM12 @ 0x009C;
/* LCD Memory 13 */
__no_init volatile unsigned char LCDM13 @ 0x009D;
/* LCD Memory 14 */
__no_init volatile unsigned char LCDM14 @ 0x009E;
/* LCD Memory 15 */
__no_init volatile unsigned char LCDM15 @ 0x009F;
/* LCD Memory 16 */
__no_init volatile unsigned char LCDM16 @ 0x00A0;
/* LCD Memory 17 */
__no_init volatile unsigned char LCDM17 @ 0x00A1;
/* LCD Memory 18 */
__no_init volatile unsigned char LCDM18 @ 0x00A2;
/* LCD Memory 19 */
__no_init volatile unsigned char LCDM19 @ 0x00A3;
/* LCD Memory 20 */
__no_init volatile unsigned char LCDM20 @ 0x00A4;
/* Display modes coded with Bits 2-4 */
#define LCDSTATIC (LCDSON)
#define LCD2MUX (LCDMX0+LCDSON)
#define LCD3MUX (LCDMX1+LCDSON)
#define LCD4MUX (LCDMX1+LCDMX0+LCDSON)
/* Group select code with Bits 5-7 Seg.lines Dig.output */
#define LCDSG0 (0x00) /* --------- Port Only (default) */
#define LCDSG0_1 (LCDP0) /* S0 - S15 see Datasheet */
#define LCDSG0_2 (LCDP1) /* S0 - S19 see Datasheet */
#define LCDSG0_3 (LCDP1+LCDP0) /* S0 - S23 see Datasheet */
#define LCDSG0_4 (LCDP2) /* S0 - S27 see Datasheet */
#define LCDSG0_5 (LCDP2+LCDP0) /* S0 - S31 see Datasheet */
#define LCDSG0_6 (LCDP2+LCDP1) /* S0 - S35 see Datasheet */
#define LCDSG0_7 (LCDP2+LCDP1+LCDP0) /* S0 - S39 see Datasheet */
/* NOTE: YOU CAN ONLY USE THE 'S' OR 'G' DECLARATIONS FOR A COMMAND */
/* MOV #LCDSG0_3+LCDOG2_7,&LCDCTL ACTUALY MEANS MOV #LCDP1,&LCDCTL! */
#define LCDOG1_7 (0x00) /* --------- Port Only (default) */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -