📄 io430x42x.h
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/********************************************************************
*
* Standard register and bit definitions for the Texas Instruments
* MSP430 microcontroller.
*
* This file supports assembler and C/EC++ development for
* MSP430x42x devices.
*
* Copyright 2004 IAR Systems. All rights reserved.
*
* $Revision: 1.3 $
*
********************************************************************/
#ifndef __IO430X42X
#define __IO430X42X
#if (((__TID__ >> 8) & 0x7F) != 0x2b) /* 0x2b = 43 dec */
#error io430x42x.h file for use with ICC430/A430 only
#endif
#ifdef __IAR_SYSTEMS_ICC__
#pragma language=extended
#ifdef __cplusplus
#define __READ /* not supported */
#else
#define __READ const
#endif
/*-------------------------------------------------------------------------
* Standard Bits
*-------------------------------------------------------------------------*/
#define BIT0 (0x0001)
#define BIT1 (0x0002)
#define BIT2 (0x0004)
#define BIT3 (0x0008)
#define BIT4 (0x0010)
#define BIT5 (0x0020)
#define BIT6 (0x0040)
#define BIT7 (0x0080)
#define BIT8 (0x0100)
#define BIT9 (0x0200)
#define BITA (0x0400)
#define BITB (0x0800)
#define BITC (0x1000)
#define BITD (0x2000)
#define BITE (0x4000)
#define BITF (0x8000)
/*-------------------------------------------------------------------------
* Status register bits
*-------------------------------------------------------------------------*/
#define C (0x0001)
#define Z (0x0002)
#define N (0x0004)
#define V (0x0100)
#define GIE (0x0008)
#define CPUOFF (0x0010)
#define OSCOFF (0x0020)
#define SCG0 (0x0040)
#define SCG1 (0x0080)
/* Low Power Modes coded with Bits 4-7 in SR */
#define LPM0_bits (CPUOFF)
#define LPM1_bits (SCG0+CPUOFF)
#define LPM2_bits (SCG1+CPUOFF)
#define LPM3_bits (SCG1+SCG0+CPUOFF)
#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
#define LPM0 _BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */
#define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */
#define LPM1 _BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */
#define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */
#define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power Mode 2 */
#define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */
#define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3 */
#define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */
#define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */
#define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */
/*-------------------------------------------------------------------------
* Special Function
*-------------------------------------------------------------------------*/
__no_init volatile union
{
unsigned char IE1; /* Interrupt Enable 1 */
struct
{
unsigned char WDTIE : 1;
unsigned char OFIE : 1;
unsigned char : 2;
unsigned char NMIIE : 1;
unsigned char ACCVIE : 1;
unsigned char URXIE0 : 1;
unsigned char UTXIE0 : 1;
} IE1_bit;
} @ 0x0000;
#define U0IE IE1 /* UART0 Interrupt Enable Register */
enum {
WDTIE = 0x0001,
OFIE = 0x0002,
NMIIE = 0x0010,
ACCVIE = 0x0020,
URXIE0 = 0x0040,
UTXIE0 = 0x0080,
};
__no_init volatile union
{
unsigned char IFG1; /* Interrupt Flag 1 */
struct
{
unsigned char WDTIFG : 1;
unsigned char OFIFG : 1;
unsigned char : 2;
unsigned char NMIIFG : 1;
unsigned char : 1;
unsigned char URXIFG0 : 1;
unsigned char UTXIFG0 : 1;
} IFG1_bit;
} @ 0x0002;
#define U0IFG IFG1 /* UART0 Interrupt Flag Register */
enum {
WDTIFG = 0x0001,
OFIFG = 0x0002,
NMIIFG = 0x0010,
URXIFG0 = 0x0040,
UTXIFG0 = 0x0080,
};
__no_init volatile union
{
unsigned char ME1; /* Module Enable 1 */
union
{
struct
{
unsigned char : 6;
unsigned char URXE0 : 1;
unsigned char UTXE0 : 1;
};
struct
{
unsigned char : 6;
unsigned char USPIE0 : 1;
};
} ME1_bit;
} @ 0x0004;
#define U0ME ME1 /* UART0 Module Enable Register */
enum {
URXE0 = 0x0040,
UTXE0 = 0x0080,
USPIE0 = 0x0040,
};
__no_init volatile union
{
unsigned char IE2; /* Interrupt Enable 2 */
struct
{
unsigned char : 7;
unsigned char BTIE : 1;
} IE2_bit;
} @ 0x0001;
enum {
BTIE = 0x0080,
};
__no_init volatile union
{
unsigned char IFG2; /* Interrupt Flag 2 */
struct
{
unsigned char : 7;
unsigned char BTIFG : 1;
} IFG2_bit;
} @ 0x0003;
enum {
BTIFG = 0x0080,
};
/*-------------------------------------------------------------------------
* Watchdog Timer
*-------------------------------------------------------------------------*/
__no_init volatile union
{
unsigned short WDTCTL; /* Watchdog Timer Control */
struct
{
unsigned short WDTIS0 : 1;
unsigned short WDTIS1 : 1;
unsigned short WDTSSEL : 1;
unsigned short WDTCNTCL : 1;
unsigned short WDTTMSEL : 1;
unsigned short WDTNMI : 1;
unsigned short WDTNMIES : 1;
unsigned short WDTHOLD : 1;
unsigned short : 8;
} WDTCTL_bit;
} @ 0x0120;
enum {
WDTIS0 = 0x0001,
WDTIS1 = 0x0002,
WDTSSEL = 0x0004,
WDTCNTCL = 0x0008,
WDTTMSEL = 0x0010,
WDTNMI = 0x0020,
WDTNMIES = 0x0040,
WDTHOLD = 0x0080,
};
#define WDTPW (0x5A00)
/* WDT-interval times [1ms] coded with Bits 0-2 */
/* WDT is clocked by fMCLK (assumed 1MHz) */
#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */
#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms */
#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms */
#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms */
/* WDT is clocked by fACLK (assumed 32KHz) */
#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms */
#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms */
#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms */
#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms */
/* Watchdog mode -> reset after expired time */
/* WDT is clocked by fMCLK (assumed 1MHz) */
#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */
#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms */
#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms */
#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms */
/* WDT is clocked by fACLK (assumed 32KHz) */
#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms */
#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms */
#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms */
#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms */
/* INTERRUPT CONTROL */
/* These two bits are defined in the Special Function Registers */
/* #define WDTIE 0x01 */
/* #define WDTIFG 0x01 */
/*-------------------------------------------------------------------------
* Hardware Multiplier
*-------------------------------------------------------------------------*/
/* Multiply Unsigned/Operand 1 */
__no_init volatile unsigned short MPY @ 0x0130;
/* Multiply Signed/Operand 1 */
__no_init volatile unsigned short MPYS @ 0x0132;
/* Multiply Unsigned and Accumulate/Operand 1 */
__no_init volatile unsigned short MAC @ 0x0134;
/* Multiply Signed and Accumulate/Operand 1 */
__no_init volatile unsigned short MACS @ 0x0136;
/* Operand 2 */
__no_init volatile unsigned short OP2 @ 0x0138;
/* Result Low Word */
__no_init volatile unsigned short RESLO @ 0x013A;
/* Result High Word */
__no_init volatile unsigned short RESHI @ 0x013C;
/* Sum Extend */
__no_init volatile unsigned __READ short SUMEXT @ 0x013E;
/*-------------------------------------------------------------------------
* Digital I/O Port1/2
*-------------------------------------------------------------------------*/
__no_init volatile union
{
unsigned __READ char P1IN; /* Port 1 Input */
struct
{
unsigned __READ char P1IN_0 : 1;
unsigned __READ char P1IN_1 : 1;
unsigned __READ char P1IN_2 : 1;
unsigned __READ char P1IN_3 : 1;
unsigned __READ char P1IN_4 : 1;
unsigned __READ char P1IN_5 : 1;
unsigned __READ char P1IN_6 : 1;
unsigned __READ char P1IN_7 : 1;
} P1IN_bit;
} @ 0x0020;
enum {
P1IN_0 = 0x0001,
P1IN_1 = 0x0002,
P1IN_2 = 0x0004,
P1IN_3 = 0x0008,
P1IN_4 = 0x0010,
P1IN_5 = 0x0020,
P1IN_6 = 0x0040,
P1IN_7 = 0x0080,
};
__no_init volatile union
{
unsigned char P1OUT; /* Port 1 Output */
struct
{
unsigned char P1OUT_0 : 1;
unsigned char P1OUT_1 : 1;
unsigned char P1OUT_2 : 1;
unsigned char P1OUT_3 : 1;
unsigned char P1OUT_4 : 1;
unsigned char P1OUT_5 : 1;
unsigned char P1OUT_6 : 1;
unsigned char P1OUT_7 : 1;
} P1OUT_bit;
} @ 0x0021;
enum {
P1OUT_0 = 0x0001,
P1OUT_1 = 0x0002,
P1OUT_2 = 0x0004,
P1OUT_3 = 0x0008,
P1OUT_4 = 0x0010,
P1OUT_5 = 0x0020,
P1OUT_6 = 0x0040,
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