fet430_tb_pwm01.c

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//*******************************************************************************
//  MSP-FET430P430 Demo - Timer_B PWM TB1-2 upmode, DCO SMCLK
//
//  Description; This program generates two PWM outputs on P2.2 and P2.3 
//  using Timer_B in an upmode.  The value in CCR0, 512, defines the period 
//  and the values in CCRx the duty PWM cycles.  Using 1048576Hz SMCLK 
//  as TBCLK, the timer period is 488us. 
//  ACLK = 32768, SMCLK = MCLK = TBCLK = 1048576Hz 
//
//               MSP430FG439
//            -----------------
//        /|\|              XIN|-  
//         | |                 | 
//         --|RST          XOUT|-
//           |                 |
//           |             P2.2|--> CCR1 - 75% PWM
//           |             P2.3|--> CCR2 - 25% PWM
//
//  M.Buccini
//  Texas Instruments, Inc
//  June 2004
//  Built with IAR Embedded Workbench Version: 2.21B
//******************************************************************************

#include <msp430xG43x.h>

void main(void)
{ 
  WDTCTL = WDTPW + WDTHOLD;             // Stop WDT
  P2DIR |= 0x0c;                        // P2.2,3 as outputs
  P2SEL |= 0x0c;                        // P2.2,3 TBx options
  TBCCR0 = 512-1;                       // PWM Period
  TBCCTL1 = OUTMOD_7;                   // CCR1 reset/set
  TBCCR1 = 384;                         // CCR1 PWM duty cycle
  TBCCTL2 = OUTMOD_7;                   
  TBCCR2 = 128;                         
               
  TBCTL = TBSSEL_2 + MC_1;              // SMCLK, up mode
  
  _BIS_SR(CPUOFF);                      // Enter LPM0
}