📄 fet430_uart01_09600.c
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//******************************************************************************
// MSP-FET430P430 Demo - USART0 UART 9600 Echo ISR, DCO SMCLK
//
// Description; Echo a received character, RX ISR used. Normal mode is LPM0,
// USART0 RX interrupt triggers TX Echo.
// ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = UCLK0 = DCOCLK = 1048576Hz
// Baud rate divider with 1048576hz = 1048576Hz/9600 ~ 109 (006Dh)
// //*An external watch crystal on XIN XOUT is required for ACLK*//
//
// MSP430FG439
// -----------------
// /|\| XIN|-
// | | | 32kHz
// --|RST XOUT|-
// | |
// | P2.4|----------->
// | | 9600 - 8N1
// | P2.5|<-----------
//
//
// M.Buccini
// Texas Instruments, Inc
// June 2004
// Built with IAR Embedded Workbench Version: 2.21B
//******************************************************************************
#include <msp430xG43x.h>
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
FLL_CTL0 |= XCAP18PF; // Configure load caps
P2SEL |= 0x30; // P2.4,5 = USART0 TXD/RXD
ME1 |= UTXE0 + URXE0; // Enable USART0 TXD/RXD
UCTL0 |= CHAR; // 8-bit character
UTCTL0 |= SSEL1; // UCLK = SMCLK
UBR00 = 0x6D; // 1MHz 9600
UBR10 = 0x00; // 1MHz 9600
UMCTL0 = 0x00; // no modulation
UCTL0 &= ~SWRST; // Initialize USART state machine
IE1 |= URXIE0; // Enable USART0 RX interrupt
P2DIR |= 0x10; // P2.4 output direction
_BIS_SR(LPM0_bits + GIE); // Enter LPM0 w/ interrupt
}
#pragma vector=UART0RX_VECTOR
__interrupt void usart0_rx (void)
{
while (!(IFG1 & UTXIFG0)); // USART0 TX buffer ready?
TXBUF0 = RXBUF0; // RXBUF0 to TXBUF0
}
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