4x4lut_sanitized.arch

用c＋＋写的用于FPGA设计中布图布线的工具源码

# NB:  The timing numbers in this architecture file have been modified
# to comply with our NDA with the foundry providing us with process 
# information.  The critical path delay output by VPR WILL NOT be accurate,
# as we have intentionally altered the delays to introduce inaccuracy.
# The numbers are still reasonable enough to allow CAD experimentation,
# though.  If you want real timing numbers, you'll have to insert your own
# process data for the various, R, C, and Tdel entries.

# Architecture with two types of routing segment.  The routing is 
# fully-populated.  One length of segment is buffered, the other uses pass
# transistors.

# Uniform channels.  Each pin appears on only one side.
io_rat 4
chan_width_io 1
chan_width_x uniform 1 
chan_width_y uniform 1

# Cluster of size 4, with 10 logic inputs.
inpin class: 0 bottom 
inpin class: 0 left
inpin class: 0 top
inpin class: 0 right
inpin class: 0 bottom 
inpin class: 0 left
inpin class: 0 top
inpin class: 0 right
inpin class: 0 bottom
inpin class: 0 left
outpin class: 1 top
outpin class: 1 right
outpin class: 1 bottom
outpin class: 1 left
inpin class: 2 global top   # Clock, global -> routed on a special resource.

# Class 0 -> logic cluster inputs, Class 1 -> Outputs, Class 2 -> clock.

subblocks_per_clb 4
subblock_lut_size 4

#parameters needed only for detailed routing.
switch_block_type subset
Fc_type fractional
Fc_output .25
Fc_input .5
Fc_pad 1

# All comments about metal spacing, etc. assumed have been deleted
# to protect our foundry.  Again, the R, C and Tdel values have been
# altered from their real values.

segment frequency: 0.5 length: 4 wire_switch: 0 opin_switch: 1 Frac_cb: 1. \
         Frac_sb: 1. Rmetal: 8.316 Cmetal: 162e-15

segment frequency: 0.5 length: 4 wire_switch: 2 opin_switch: 2 Frac_cb: 1. \
         Frac_sb: 1. Rmetal: 8.316 Cmetal: 162e-15

# Pass transistor switch.

switch 0  buffered: no  R: 196.728 Cin: 20.574e-15  Cout: 20.574e-15 Tdel: 0

# Logic block output buffer used to drive pass transistor switched wires.

switch 1  buffered: yes  R: 393.47 Cin: 7.512e-15  Cout: 20.574e-15 \
       Tdel: 524e-12

# Switch used as a tri-state buffer within the routing, and also as the
# output buffer used to drive tri-state buffer switched wires.

switch 2  buffered: yes  R: 786.9 Cin: 7.512e-15  Cout: 10.762e-15 \
       Tdel: 456e-12

# Used only by the area model.

R_minW_nmos 1967
R_minW_pmos 3738

# Timing info below.  See manual for details.

C_ipin_cblock 7.512e-15

T_ipin_cblock 1.5e-9

T_ipad 478e-12   # clk_to_Q + 2:1 mux
T_opad 295e-12   # Tsetup
T_sblk_opin_to_sblk_ipin 1096e-12
T_clb_ipin_to_sblk_ipin 693e-12
T_sblk_opin_to_clb_opin 0.

# Delays for each of the four sequential and combinational elements
# in our logic block.  In this case they're all the same.

T_subblock T_comb: 546e-12 T_seq_in: 845e-12 T_seq_out: 478e-12
T_subblock T_comb: 546e-12 T_seq_in: 845e-12 T_seq_out: 478e-12
T_subblock T_comb: 546e-12 T_seq_in: 845e-12 T_seq_out: 478e-12
T_subblock T_comb: 546e-12 T_seq_in: 845e-12 T_seq_out: 478e-12