descript.txt

用c＋＋写的用于FPGA设计中布图布线的工具源码

Version 4.00, Beta #6, Nov. 5, 1997

- Added code to build a timing graph of the circuit and do path analysis.  
  Both the critical path and all the net slacks are determined.

- Split the code that checks the netlist for validity off into a separate 
  module, check_netlist.  Beefed up the error checking so that all the 
  connections between subblocks and clbs and amongst subblocks are checked 
  for errors.

- Changed the net_pin_class data structure to the net_block_pin_num data 
  structure -- it now stores the pin number to which the netlist says each net 
  should connect at a certain block.  For routing I really just have to connect
  to a pin of this *class* on the specified block, but for timing analysis I 
  really need to know the actual pin specified to build the timing graph 
  correctly.  For the places where I want to check the class of what I have
  to connect to, I just have to take clb_pin_class[pnum], where pnum comes from
  this new structure.

- Changed the timing analysis parameters specified in the architecture file
  to make them easier to understand and more flexible.  Each subblock can 
  now have its own delays (different from that of other subblocks).

- Changed the input netlist format slightly so that subblock outputs that 
  are routed within a subblock to the inputs of other subblocks don't have 
  to connect to any clb output pin.


Version 4.00, Beta #5, Sept. 19, 1997:

- Made an Elmore-delay based net delay calculator (in net_delay.c).

- Restructured routing_stats (in stats.c) slightly to make the control routine
  simpler.

- Sept. 19, 1997:  Incorporated Zoom Fit code of Haneef Mohammed at Cypress.  
  Makes it easy to zoom to a full view of the graphics. 


Version 4.00, Beta #4, Sept. 12, 1997:

- Added a Congestion button to the graphics display.  It shows all the 
  overused routing resources in red.  This required some changes to 
  graphics.c to allow buttons to be created and deleted on the fly.

- Made the coordinates (e.g, 4,3) of the block you click on appear in the
  text area of the graphics display.  Requested by Jordan and Yaska.


Version 4.00, Beta #3, August 28, 1997:

- Added code to make VPR suitable as a CPU benchmark for the SPEC consortium.
  Add the line -DSPEC in the makefile to turn on the SPEC code.  Normal 
  users of VPR should never define SPEC, so you can ignore all the code
  after an #ifdef SPEC line.

  The SPEC specific stuff doesn't do much -- it just rips out the
  graphics and makes sure different roundoff behaviour on different
  machines doesn't lead to different routings.

- Added a "NO_GRAPHICS" define.  If you define NO_GRAPHICS in pr.h, all the 
  X11 code is ripped out allowing VPR to be compiled on machines without X11 
  graphics.

- Wrote my own random number generation routine, based on rand.  It's tuned
  for speed, not spectral quality.  This lets me get rid of the ARCH_TYPE
  flag, and makes the code more portable across architectures.

- Added a segment usage statistics routine.  This routine needs to know
  what the type and length of each track of an FPGA is.  The rr_graph
  builder saves that information once it has built the graph.  If you don't
  want to generate this extra information (because you're building your
  own graph), just don't call the segment usage routine after routing.

- Moved around some of the rr_graph data elements.  rr_node_draw_inf is 
  now gone -- .type and .ptc_num are now part of rr_node.  rr_node gives all
  the physical information about a node except its capacity (which is still
  in rr_node_cost_inf).  I also moved .prev_node, .prev_edge, .cost, 
  .target_flag, and .path_cost to a new structure, rr_node_route_inf.  This
  structure is local to the router, and is allocated, initialized and freed
  by the router, so you don't have to worry about it.  Just load up 
  rr_node and rr_node_cost_inf in the rr_graph.c routines.

- Added a transistor based area model.  It goes through the rr_graph and
  figures out how many minimum width transistor areas are needed to build the
  FPGA routing.

- Changed rr_graph generator so that pass transistors always create two edges 
  in the graph.  This makes the area model etc. a lot easier.


Version 4.00, Beta #2, July 15, 1997:

- Changed rr_graph so that IO pads now have all the switches necessary to
  be both an input pad and an output pad built.  The EMPTY_PAD rr_type has
  been eliminated.  This change doesn't make any difference to the router,
  but it will give more accurate transistor counts.

- Changed the rr_graph to allow each switch coming off a node to be a 
  different type.  Changed the architecture definition file format so that
  each .segment line specifies the type of switch used by a wire to drive 
  that segment, and the type of switch used by an output pin to drive that
  segment.


Version 4.00, Beta #1, July 3, 1997:

- Removed router limitation that it couldn't route more than 1 pin of a net
  to the same sink (same pin class on a logic block).  For the LUT-based
  logic blocks I look at there should never be more than one pin from a net
  to any sink, but for other logic blocks this could occur.  I still warn
  the user about this though, since most logic blocks shouldn't have this
  feature.  I sped up the check for multiple connections to a sink (in
  read_netlist) as well.

- Added ability to graphically see which switches are buffers and which are
  pass transistors.

- Added some of the hooks for timing analysis (capacitance loader, timing
  parameter parser, etc.)

- Added routing graph sanity checker.

- Added segmentated architecture for routing.

- Fixed the read_netlist bug where the parser would complain if a subblock
  line started with white space (noticed by Kevin Skahill at Cypress).

Version 3.99a

- Added -fast option, and -route_chan_width option.  -route_chan_width
  option allows only one routing to be done, rather than a binary search.

- Fixed fact that bounding box clipping of the routing region was too
  aggressive (noticed by Russ Tessier).

Version 3.99

- Added D. F. Wong's Universal switch block as one of the switch blocks
  supported.

- Code cleanup.  Put the placer options in a placer_opts structure, and 
  moved the input and output code from place.c to read_place.c.

- Added the ability to read in the location of the IO pads and force the
  placer to keep them there.

- Changed the placement output format slightly.  Block numbers are now
  only in comments.  The placement input parser was completely rewritten.
  Comments and line continuation are now allowed in placement files.  More
  importantly, the order of the blocks is now irrelevant; the file can list
  the blocks in any order.  This should be a lot more convenient for people
  using VPR to route placements generated by other tools.  The error 
  checking has been beefed up too -- I think every possible error in a 
  placement file will be caught now and the user will get an informative
  error message.  In particular, the "non-consecutive subblock" error that
  tripped up Russ and Ivan will be caught right away.

- Moved all hash table logic out of read_netlist.c and into a new module,
  hash.c.  I can use this general hash table stuff all over now.

- Changed defaults to be 30 routing iterations and detailed routing.

- Changed VPR to use a graph-based model of the routing resources available.
  This allows VPR to perform either global or detailed routing now.  Also
  added new graphics options to view the routing resources available.
  Took the routing checker out of route.c and put it in check_route.c.
  Also moved some code from route.c to stats.c.

- Converted some defined constants to enumerated types so I can see the
  symbolic names in gdb.

- Cleaned up some of the placer code.  Centralized allocation of the temporary
  placement data structures.  Changed the standard deviation computation
  so that the old_costs array wasn't needed anymore.

Version 3.98a

- Made a minor change to the graphics package.  Descenders (e.g. "g")
  are now considered in the vertical text centering routines.

- Changed the placer inner loop so that the frequency with which recompute
  cost is called is variable.  Recomputing the cost from time to time
  from scratch stops round offs from accumulating.  The change didn't make
  VPR significantly faster.

- Made -inner_num a float to allow small inner nums to be tried.

- Code cleanup.  Converted the annealing schedule parameters from 
  global variables to a structure that is passed around.  Converted the
  graphics state from global variables to static variables in draw.c set
  via a call to set_graphics_state.

- Added -verify_binary_search option.  Makes the router try routings
  with channel widths of best-2 and best-3 (in addition to the best-1
  tried by the binary search).  If one of these additional routings
  succeeds, the router keeps trying routings until two in a row (e.g.
  width = 9 and width = 8) fail.  The binary search usually finds the
  min. channel width, but due to router flukiness it will occassionally
  happen that a width = 19 routing fails, but width = 18 succeeds and
  so on.
 
Version 3.98

- Changed initial routing channel width guess to clb_size (# of pins
  on a clb).  Should give slightly faster run times for big clbs.

- Fixed a bug where VPR would wrongly think it had an error and 
  terminate itself if two outputs were made logically equivalent.
  Bug noticed by George Varghese of UC Berkeley.

- Altered VPR to use the new netlist format of blifmap (cluster-based).
  In this process I fixed a minor netlist parsing bug where VPR would
  refuse to accept a netlist with a comment between a .clb and a .pinlist
  line.  The new information on what's in a cluster is in the .subblock
  lines following each .clb line (after the .pinlist line).

Version 3.23

NB:  May want to add check in read_place for subblock numbers that have
  gaps (not consecutive starting at zero).  Russ Tessier's suggestion.
  (I did this on March 22, 1997 -- Version 3.99).

- Updated graphics again -- made all internal functions static so that
  graphics.c is a true component without name space conflicts with user
  programs.  Also moved the toggle_nets function to draw.c, as this 
  cleaned up the code dependencies a bit.

- Corrected RISA reference in the source code to point to ICCAD (pointed
  out by Russ Tessier of MIT).

- Rewrote large parts of graphics package.  It should now be faster for
  zoomed in graphics, as it preclips them based on their bounding box. 
  This will also make zoomed-in postscript much smaller.  The PostScript
  driver has been rewritten; output file sizes are about 50% smaller now
  if all graphics are on-screen.  When zoomed-in the clipping makes an
  even bigger difference.  Also added the ability to specify the font size
  for text and the line width for geometry (I demand-load the fonts
  for maximum efficiency while hiding details like font loading from the
  calling program).  Finally, I removed the global drawscreen function
  and replaced it with a callback function to clean up the code a bit.
  

Version 3.22

- Changed some code in util.c that HP's C compiler didn't like. 
  Turned on all warning options in gcc and fixed all warnings,