rdac_latch.mdf

Proteus+7.8+元件库

LISA MODEL DESCRIPTION FORMAT 6.0
=================================
Design:   C:\Program Files\Labcenter Electronics\VSM.LIBS\VSM.LIBS SAMPLES\DIGITAL POTS\RDAC LATCHES\RDAC_LATCH.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author:   <NONE>
Created:  30/10/03
Modified: 30/12/03

*PROPERTIES,1    
POTVAL=<POTVAL>

*MODELDEFS,0    

*PARTLIST,11   
AVS1,AVS,"1.0*V(A,B)",PRIMITIVE=ANALOGUE
AVS2,AVS,"5-V(A,B)",PRIMITIVE=ANALOGUE
DAC1,DAC_8,DAC_8,MODDLL=DATAC,MODE=UNSIGNED,PRIMITIVE=PASSIVE,SLEWRATE=1E6,TDDA=0
G3FADCE08,VDC!,5.0,HIDDENPROPS=TRUE,MANUALEDITS=FALSE,PRIMITIVE=PROBE
M3FADCE08,VPROBE,DAC1(VREF+),PRIMITIVE=PROBE
R1,RESISTOR,10k,PRIMITIVE=ANALOGUE
R2,RESISTOR,1T,PRIMITIVE=ANALOGUE
R3,RESISTOR,1T,PRIMITIVE=ANALOGUE
R4,RESISTOR,1T,PRIMITIVE=ANALOGUE
S1,VCR,VCR,PRIMITIVE=ANALOGUE,ROFF=<POTVAL>,RON=1u,VOFF=0,VON=5
S2,VCR,VCR,PRIMITIVE=ANALOGUE,ROFF=<POTVAL>,RON=1u,VOFF=0,VON=5

*NETLIST,18   
#00000,2
AVS1,PS,+
S2,PS,P

#00001,4
AVS1,PS,A
AVS2,PS,A
DAC1,PS,VOUT
R1,PS,1

#00002,2
AVS2,PS,+
S1,PS,P

#00003,3
DAC1,PS,VREF+
G3FADCE08,OP,*
M3FADCE08,IP,*

GND,9
GND,PR
AVS1,PS,-
AVS2,PS,-
AVS1,PS,B
AVS2,PS,B
DAC1,PS,VREF-
R1,PS,2
S1,PS,N
S2,PS,N

LE,2
LE,IT
DAC1,IP,LE

D0,2
D0,IT
DAC1,IP,D0

D1,2
D1,IT
DAC1,IP,D1

D2,2
D2,IT
DAC1,IP,D2

D3,2
D3,IT
DAC1,IP,D3

D4,2
D4,IT
DAC1,IP,D4

D5,2
D5,IT
DAC1,IP,D5

D6,2
D6,IT
DAC1,IP,D6

D7,2
D7,IT
DAC1,IP,D7

B,3
B,GT
S1,PS,+
R2,PS,2

W,4
W,GT
S1,PS,-
S2,PS,-
R3,PS,1

A,3
A,GT
S2,PS,+
R4,PS,2

AGND,4
AGND,GT
R2,PS,1
R3,PS,2
R4,PS,1

*GATES,0