syslib.c

vworks 下wlan的实现代码

    mbxI2cConfigParamsGet();

    /* internal clock rate in MHZ */

    sysMbxIntClkSpd = *(int *)(DPRAM_INT_CLK_SPD);

    /* Reference clock speed */

    sysRefClkFrq = *(int *)(DPRAM_REF_CLK_FRQ);

    /* external clock rate in MHZ */

    sysMbxExtClkSpd = *(int*)(DPRAM_EXT_CLK_SPD);

    /* PCI Bus Bridge device present? */

    sysQspanPresent = *(BOOL *)(DPRAM_QSPAN_PRSNT);

    /* On-board DRAM size */

    sysDramSize = *(int *)(DPRAM_DRAM_SIZE);

    /* On-board DRAM speed */

    sysDramSpd =  *(int *)(DPRAM_DRAM_SPD);

    /* DIMM size */

    sysDimmSize =  *(int *)(DPRAM_DIMM_SIZE);

    /* Flash memory size */

    sysFlashSize =  *(int *)(DPRAM_FLASH_SIZE);

    /* determines where boot is running from */

    sysBootType = *(int *)(DPRAM_BOOT_TYPE);

    /* store the total RAM size for the board */

    sysRamSize = *(UINT *)(DPRAM_TOTAL_RAM_SIZE);

    /* update the sysPhysMemDesc table to allow for entire RAM size */

#if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL)
    sysPhysMemDesc[0].len = sysRamSize;
#endif

    /* clear the additional Ram space */

#ifdef LOCAL_MEM_AUTOSIZE
    if (sysStartType == BOOT_COLD)
        bfill( (char *)(LOCAL_MEM_LOCAL_ADRS+LOCAL_MEM_SIZE),
	   (sysRamSize - LOCAL_MEM_SIZE), 0 );
#endif

    /* 
     * Now that the internal clock rate is known, setup the timer 
     * variables and the global clock frequency variables.
     */

    spllMulFactor = ((sysMbxIntClkSpd / sysRefClkFrq)-1);
    spllFreq = ((spllMulFactor + 1) * sysRefClkFrq);
    brgClkFreq = (spllFreq / ( 1 << ( 2 * BRGCLK_DIV_FACTOR )));
    refreshValue = (brgClkFreq / DRAM_REFRESH_FREQ);
    ptaValue = (refreshValue / PTP_DIVISOR);


    /* set the SPLL to the value requested */
    /* SPR 65678, wrap PLPRCR, SCC in unlock/lock code */
#ifdef USE_KEYED_REGS
    /* Set global variable to be true so vxWorks code does uses key registers*/
    vx860KeyedRegUsed=TRUE;

    * PLPRCRK(immrVal) = KEYED_REG_UNLOCK_VALUE;
    ISYNC;
#endif

    plprcrVal= 	((*PLPRCR(immrVal) & ~PLPRCR_MF_MSK) | 
                 (spllMulFactor << PLPRCR_MF_SHIFT));
    /* clocks used up after PLPRCR is set (delay * 16) + 2 clocks */
    vxPlprcrSet ( (UINT32*)immrVal ,plprcrVal ,3 /*delay*/);

#ifdef USE_KEYED_REGS
    * PLPRCRK(immrVal) = ~KEYED_REG_UNLOCK_VALUE;
#endif

    /* set the BRGCLK division factor */

#ifdef USE_KEYED_REGS
    * SCCRK(immrVal) = KEYED_REG_UNLOCK_VALUE;
    ISYNC;
#endif

    * SCCR(immrVal) = (* SCCR(immrVal) & ~SCCR_DFBRG_MSK) |
				(BRGCLK_DIV_FACTOR << SCCR_DFBRG_SHIFT);

    /* set the TimeBase source */

    * SCCR(immrVal) |= SCCR_TBS;		/* System Clock / 16 */

    /* 
     * Set the RTC circuit input source select to OSCM
     * Set RTC and PIT clock divided by 4 */

    *SCCR(immrVal) &= ~(SCCR_RTSEL | SCCR_RTDIV);
#ifdef USE_KEYED_REGS
    * SCCRK(immrVal) = ~KEYED_REG_UNLOCK_VALUE;
#endif

    /* set the Periodic Timer A value */
     
    * MAMR(immrVal) = (* MAMR(immrVal) & ~MAMR_PTA_MSK) | 
				(ptaValue << MAMR_PTA_SHIFT);	

    /* set the Periodic Timer PreScale */

    * MPTPR(immrVal) = PTP_VALUE;

    /* reset the port A */

    *PAPAR(immrVal) = 0x0000;
    *PADIR(immrVal) = 0x0000;
    *PAODR(immrVal) = 0x0000;

    /* reset the port B */

    *PBPAR(immrVal) = 0x0000000;
    *PBDIR(immrVal) = 0x0000000;
    *PBODR(immrVal) = 0x0000000;

    /* reset the port C */

    *PCPAR(immrVal) = 0x0000;
    *PCDIR(immrVal) = 0x0000;
    *PCSO(immrVal)  = 0x0000;

    /* reset the port D */

    *PDPAR(immrVal) = 0x0000;
    *PDDIR(immrVal) = 0x0000;

    *SICR(immrVal) = 0x0;		/* initialize SI/NMSI connections */

    /* disable the RTC */
#ifdef USE_KEYED_REGS
    *RTCSCK(immrVal) = KEYED_REG_UNLOCK_VALUE;
    ISYNC;
#endif
    *RTCSC(immrVal) = (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF);
#ifdef USE_KEYED_REGS
    *RTCSCK(immrVal) = ~KEYED_REG_UNLOCK_VALUE;
#endif

#ifdef	INCLUDE_CPM_END
    /* store the boards ethernet address into sysCpmEnetAddr */

    for (i=0; i<6; i++)
	sysCpmEnetAddr[i] = *(UCHAR *)(DPRAM_ENET_ADDR + i);
#endif	/* INCLUDE_CPM_END */

    /* Install sysMbxInt* routines as the system int* routines */

    _func_intConnectRtn = sysMbxIntConnect;
    _func_intEnableRtn  = sysMbxIntEnable;
    _func_intDisableRtn = sysMbxIntDisable;

    /* Initialize interrupts */

    ppc860IntrInit (IV_LEVEL4);	/* default vector level */

    /* Disable Ethernet */

#ifdef	INCLUDE_CPM_END
    sysCpmEnetDisable (0);
    sysCpmEnetIntDisable (0);
#endif	/* INCLUDE_CPM_END */

    /*
     * The power management mode is initialized here. Reduced power mode
     * is activated only when the kernel is iddle (cf vxPowerDown).
     * Power management mode is selected via vxPowerModeSet().
     * DEFAULT_POWER_MGT_MODE is defined in config.h.
     */

    vxPowerModeSet (DEFAULT_POWER_MGT_MODE);

    /*
     * Download I2C/SPI RISC microcode patch
     *
     * MUST RE-MAP THE I2C INTO IDMA1 at 0x1cc0 
     * with the following patch.
     */

    i2cMcp();

    /*
     * Enable external synchronous bus masters, enable retry
     *
     * initialize the QBus-to-PCIBus bridge controller device,
     * if the device is present
     *
     * verify that the appropriate chip select is enabled, and
     * if the chip select is enabled, probe the device for its
     * identifiers
     *
     * initialize the PCI device probe list with the ROM built-in
     *
     * call the PCI device probe/configure function
     */

#ifdef INCLUDE_PCI
    if (sysQspanPresent) 
	{
	qspanAdr = ((*BR6(immrVal)) & BR_BA_MSK);  /* Get Qspan Addr */

        QSPAN_READ(qspanAdr+QSPAN_PCI_ID, temp);
        if ( temp == PCI_ID_QSPAN)
            {
            /* initialize the QSpan device */

            qspanHostInit(qspanAdr);
            qspanHostEnable(qspanAdr);

	    /* Initialize PCI driver library.  */

	    if (sysQspanRevisionId < QSPAN_REVISION_1_2)
		{

		/* 
		 * make a call to initialize the PCI driver library.
		 *
		 * for the older versions of the QSPAN chip, we have to
		 * install the machine check exception handler as part
		 * of the PCI read or write call.
		 */

		if (pciConfigLibInit (PCI_MECHANISM_0, (ULONG) sysPciCfgRead, 
				 (ULONG) sysPciCfgWrite,0) != OK)
		    {
		    sysToMonitor (BOOT_NO_AUTOBOOT);
		    }
		}
	    else
		{

		/* 
		 * for QSPAN 1.2 and above we enable the MA_BE_D bit in
		 * the MISC_CTL register, which provides normal 
		 * termination to the Processor Bus, and therefore we
		 * can use the generic PCI read/write calls.
		 */

		if (pciConfigLibInit (PCI_MECHANISM_1, PCI_PRIMARY_CAR,
				PCI_PRIMARY_CDR, 0) != OK)
		    {
		    sysToMonitor (BOOT_NO_AUTOBOOT);
		    }
		}

	    /* Initialize the Standard PCI Header of the ... device */

	    if (pciFindDevice ((PCI_ID_W83C553F & 0xFFFF),
	                       (PCI_ID_W83C553F >> 16) & 0xFFFF, 0,
	                       &pciBusNo, &pciDevNo, &pciFuncNo) != ERROR)
		{
		(void)sysIbcPciExtInit(pciBusNo, pciDevNo, pciFuncNo);

		sysIbcInit();
		}

            /* find the Winbond EIDE/ATA device */

            if (pciFindDevice ((PCI_ID_SL82C105 & 0xFFFF),
                               (PCI_ID_SL82C105 >> 16) & 0xFFFF, 0,
                               &pciBusNo, &pciDevNo, &pciFuncNo) != ERROR)
                {
                (void) sysAtaInit(pciBusNo, pciDevNo, pciFuncNo);
                }

	    /*  Add Additional devices here START      */

	    /*  Add Additional devices here END        */

	    /* initialize the PC-I/O peripherals device (SMC FDC37C932) */

	    smcC67Init();
	    }
	}
#endif /* INCLUDE_PCI */

    /* Reset serial channels */

    sysSerialHwInit();
    }

#ifdef INCLUDE_PCI

/******************************************************************************
*
* sysPciCfgRead - read longword from PCI configuration space
*
* This does a QSPAN style PCI read.  This function is passed as a pointer 
* during initialization of PCI mechanism 0 in pciConfigLibInit.  This 
* function has the machine check handler support included in.
*
* RETURNS: OK always.
*/

STATUS sysPciCfgRead
    (
    int busNo,
    int deviceNo,
    int funcNo,
    int offset,
    int size, /* 1, 2, or 4 */
    void * pResult
    )
    {
    FUNCPTR     machCheckHandler;
    IMPORT int  pciConfigBdfPack(int bus, int dev, int func);
    int         key;
    STATUS      result = OK;
    UINT32      conAdrVal;
    UINT32      conDataReg;

    /* generate coded value for CON_ADR register */

    conAdrVal = pciConfigBdfPack (busNo, deviceNo, funcNo) | (offset & 0xfc);
    conDataReg = (UINT32)PCI_PRIMARY_CDR + (offset & 0x3);

    /* Use Type 1, if bus is not the local bus */

    if (busNo != PCI_HOST_BUS_NBR)
        conAdrVal |= 0x1; /* do type 1 for other busses */

    /*
     * Connect the PowerPC machine check exception to catch exceptions,
     * Save off the existing handler first.
     * NOTE:  The QSpan PCI Bridge causes machine check exceptions to
     * occur when a non-present device address is put into the
     * configuration register.
     */

    machCheckHandler = excVecGet ((FUNCPTR *) _EXC_OFF_MACH);

    key = intLock ();

    /* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */

    PCI_OUT_LONG (PCI_PRIMARY_CAR, conAdrVal);

    excVecSet ((FUNCPTR *) _EXC_OFF_MACH, (FUNCPTR)sysPciTrap);


    switch (size)
	{
	case 4:
	    /* Note: *pResult comes back as -1 if machine check happened */

	    if ( (*(UINT32 *)pResult = PCI_IN_LONG (conDataReg)) == 0xffffffff)
		result = ERROR;
	    break;

	case 2:

	    if ((*(UINT16 *)pResult = PCI_IN_WORD (conDataReg)) == 0xffff)
		result = ERROR;
	    break;

	case 1:

	    if ((*(UCHAR *)pResult = PCI_IN_BYTE (conDataReg)) == 0xff)
		result = ERROR;
	    break;

	default:

	    result = ERROR;
	    break;
	}

    /* Restore the PowerPC machine check exception */

    excVecSet ((FUNCPTR *) _EXC_OFF_MACH, (FUNCPTR)machCheckHandler);

    intUnlock (key);

    return (result);
    }


/******************************************************************************
*
* sysPciCfgWrite - write longword to PCI configuration space
*
* This does a QSPAN style PCI write.  This function is passed as a pointer
* during initialization of PCI mechanism 0 in pciConfigLibInit.  This 
* function has the machine check handler support included in.
*
* RETURNS: OK always
*/

STATUS sysPciCfgWrite
    (
    int busNo,
    int deviceNo,
    int funcNo,
    int offset,
    int size,
    UINT32 data
    )
    {
    FUNCPTR     machCheckHandler;
    IMPORT int  pciConfigBdfPack(int bus, int dev, int func);
    int         key;
    STATUS      result = OK;
    UINT32      conAdrVal;
    UINT32      conDataReg;

    conAdrVal = pciConfigBdfPack (busNo, deviceNo, funcNo) | (offset & 0xfc);
    conDataReg = PCI_PRIMARY_CDR + (offset & 0x3);

    if (busNo != 0)
        conAdrVal |= 0x1; /* do type 1 for other bus */

    /*
     * Connect the PowerPC machine check exception to catch exceptions,
     * Save off the existing handler first.
     * NOTE:  The QSpan PCI Bridge causes machine check exceptions to
     * occur when a non-present device address is put into the
     * configuration register.
     */

    key = intLock ();

    machCheckHandler = excVecGet ((FUNCPTR *) _EXC_OFF_MACH);

    PCI_OUT_LONG (PCI_PRIMARY_CAR, conAdrVal);

    excVecSet ((FUNCPTR *) _EXC_OFF_MACH, (FUNCPTR)sysPciTrap);

    switch (size)
	{
	case 4:
	    PCI_OUT_LONG (conDataReg, (UINT32)data);
	    break;

	case 2:
	    PCI_OUT_WORD (conDataReg, (UINT16)data);
	    break;

	case 1:
	    PCI_OUT_BYTE (conDataReg, (UINT8)data);
	    break;

	default:
	    result = ERROR;
	    break;
	}

    /* Restore the PowerPC machine check exception */

    excVecSet ((FUNCPTR *) _EXC_OFF_MACH, (FUNCPTR)machCheckHandler);

    intUnlock (key);

    return (result);
    }
#endif

/*******************************************************************************
*
* sysPhysMemTop - get the address of the top of physical memory
*
* This routine returns the address of the first missing byte of memory,
* which indicates the top of memory.
*
* RETURNS: The address of the top of physical memory.
*
* SEE ALSO: sysMemTop()
*/