syslib.c

vworks 下wlan的实现代码

/* sysLib.c - Motorola MBX860 board system-dependent library */

/* Copyright 1984-2002 Wind River Systems, Inc. */
/* Copyright 1997,1998 Motorola, Inc., All Rights Reserved */
#include "copyright_wrs.h"

/*
modification history
--------------------
01y,08jul02,dtr  Adding windML support.
01x,17may02,dtr  Changing INCLUDE_AUXCLK to INCLUDE_AUX_CLK.
01w,09may02,dtr  Adding in fix for SPR 34619. MPC860 Errata.
01v,04mar02,dtr  Adding ppc860Timer. This driver includes auxClk and timestamp.
01u,30jan02,dtr  Removing compiler warnings.
01t,15nov01,dtr  Fixing sysToMonitor. SPR 29853.
01s,16oct01,dtr  Putting in fix for SPR65678 plus mod history.
01q,09apr01,rip  wrap of keyed register writes with unlock/lock code (SPR 65678)
01r,16sep01,dat  Use of WRS_ASM macro
01q,13jul00,db   Conditional inclusion of PCI related code(SPR #24790).
01p,10feb99,tm   Updated Mechanism 0 PCI I/O routines to new API (SPR 24846)
01o,09feb99,mas  Removed erroneous Guard bit in ROM memory region (SPR 21923)
01n,03dec98,mas  added GUARDED attributes to non-local memory areas mapped in
		 sysPhysMemDesc[]. (SPR 23674)
01m,31jul98,rhk  modified the way the PCI library is initialized, based on
		 the revision number of the QSPAN on the board.
01l,30jun98,rhk  merged versions of WRS and MCG files.
01k,10jun98,dat  converted pciConfigBDFPack to pciConfigBdfPack(), chg'd arg
		 types for sysInXxxx() and sysOutXxxx().
01j,08may98,map  cleanup macros
01i,07apr98,dat  fixed sysPhysMemDesc
01h,31mar98,map  Removed "#include ataDrv.c"
01g,30mar98,map  assert TBF bit in TBSCR to stop decrementer, and timebase
                 when freeze is asserted.
01f,26mar98,map  code cleanup.
01e,14mar98,rhk  added sysPciCfgRead and sysPciCfgWrite, moved machine
		 check handler into these routines, changed to support
		 pciConfig* files.
01d,19nov97,rhk  WRS code review cleanup.
01c,27sep97,scb  Modified for crystal or 1:1 oscillator input clock.
01b,25aug97,srr  replaced including of pci.h with drv/pci/pciIomapLib.h
01a,12may97,srr  modified for MBX boards.
*/

/*
DESCRIPTION
This library provides board-specific routines.  The chip drivers included are:

    ppc860Timer.c	- PowerPC Decrementer Timer library + 860 timers.
    ppcDecTimer.c	- PowerPC Decrementer Timer library.
    byteNvRam.c		- NVRAM access routines
    mbxI2c.c          	- I2C bus access
    qspanPci.c		- QSPAN PCI bus bridge device
    w83c553f.c        	- ISA interrupt controller
    smcC67SuperIo.c 	- Super I/O chip initialization
    i2cMcp.c          	- I2C micro-chip patch
    ataDrv.c          	- IDE/ATA driver
    mbxPcmcia.c        	- PCMCIA support
    mbxLptDrv.c         - Parallel port driver
    fdcDrv.c		- Floppy driver


INCLUDE FILES: sysLib.h

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include "vxWorks.h"
#include "vme.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "string.h"
#include "intLib.h"
#include "logLib.h"
#include "stdio.h"
#include "taskLib.h"
#include "vxLib.h"
#include "tyLib.h"
#include "drv/pci/pciConfigLib.h"
#include "arch/ppc/vxPpcLib.h"
#include "private/vmLibP.h"
#include "drv/pcmcia/pccardLib.h"
#include "drv/hdisk/ataDrv.h"

#include "drv/multi/ppc860Siu.h"
#include "drv/sio/ppc860Sio.h"
#include "mbx800.h"

#include "qspanPci.h"		/* QBus-to-PCIBus bridge device */

#include "esf.h"
#include "excLib.h"

/* externals */

IMPORT void	i2cMcp();	/* download I2C/SPI RISC microcode patch */
IMPORT void 	smcC67Init();	/* initialize PC-I/O peripherals device */
IMPORT void	qspanHostInit(register UINT32 baseAddr);
				/* PIRQ[0:3] route control regs I/O control */
IMPORT void	qspanHostEnable(register UINT32 baseAddr);
IMPORT short	sysInWordRev();
IMPORT int	sysPciErr();
IMPORT int	sysDecGet();
IMPORT STATUS	sysPciCfgRead();
IMPORT STATUS	sysPciCfgWrite();
IMPORT int	sysStartType;
IMPORT int	sysQspanRevisionId;
IMPORT UINT32   vx860KeyedRegUsed;
IMPORT void     vxPlprcrSet (UINT32*,UINT32,UINT32);
/*IMPORT STATUS mbxPcmciaConfig ();*/

/* Macro for all i/o operations to use */

#define SYNC   WRS_ASM(" sync")
#define ISYNC  WRS_ASM(" isync")

#define PCI_HOST_BUS_NBR        0       /* number of bus on far side of  */
					/* Host-PCI bridge */

PHYS_MEM_DESC sysPhysMemDesc [] =
    {
    {
    (void *) LOCAL_MEM_LOCAL_ADRS,
    (void *) LOCAL_MEM_LOCAL_ADRS,
    LOCAL_MEM_SIZE ,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE
    },

    {
    /* PCI I/O window, includes the ISA I/O window */
    (void *) PCI_MSTR_IO_LOCAL,
    (void *) PCI_MSTR_IO_LOCAL,
    PCI_MSTR_IO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    {
    /* PCI MEM window, includes the ISA MEM window */
    (void *) PCI_MSTR_MEM_LOCAL,
    (void *) PCI_MSTR_MEM_LOCAL,
    PCI_MSTR_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    {
    /* NVRAM window */
    (void *) NV_RAM_BA,
    (void *) NV_RAM_BA,
    NV_RAM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    {
    /* Board control register */
    (void *) BCSR1,
    (void *) BCSR1,
    0x00001000,				/* 4 k - Board Control and Status */	
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    {
    (void *) INTERNAL_MEM_MAP_ADDR,
    (void *) INTERNAL_MEM_MAP_ADDR,
    INTERNAL_MEM_MAP_SIZE,		/* 64 k - Internal Memory Map */	
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    {
    /* PCI Host bridge, on local bus */
    (void *) CPU_PCI_BRIDGE_BA,
    (void *) CPU_PCI_BRIDGE_BA,
    CPU_PCI_BRIDGE_SIZE,		/* 64 k - Internal Memory Map */	
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

#ifdef INCLUDE_MBX_PCMCIA			/* include PCMCIA driver */
#ifdef INCLUDE_WLAN_END
    {
    (void *) PCMCIA_ATTRIBUTE_BA,
    (void *) PCMCIA_ATTRIBUTE_BA,
    PCMCIA_ATTR_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    {
    (void *) PCMCIA_IO_BA,
    (void *) PCMCIA_IO_BA,
    PCMCIA_IO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },
#else
    {
    (void *) PCMCIA_MEMORY_BA,
    (void *) PCMCIA_MEMORY_BA,
    PCMCIA_SIZE,			/* PCMCIA memory */	
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },
#endif /* INCLUDE_PRISM_END */
#endif /* INCLUDE_MBX_PCMCIA */

    {
    /* Flash window */
    (void *) ROM_BASE_ADRS,
    (void *) ROM_BASE_ADRS,
    ROM_SIZE,				/* Flash memory */	
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    }
    };

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

int   sysBus      = BUS;                /* system bus type (VME_BUS, etc) */
int   sysCpu      = CPU;                /* system CPU type (PPC860) */
char *sysBootLine = BOOT_LINE_ADRS;	/* address of boot line */
char *sysExcMsg   = EXC_MSG_ADRS;	/* catastrophic message area */
int   sysProcNum;			/* processor number of this CPU */
int   sysFlags;				/* boot flags */
char  sysBootHost [BOOT_FIELD_LEN];	/* name of host from which we booted */
char  sysBootFile [BOOT_FIELD_LEN];	/* name of file from which we booted */
BOOL  sysVmeEnable = FALSE;		/* by default no VME */
int   sysMbxIntClkSpd = FREQ_25_MHZ;	/* internal clock rate in MHZ */
int   sysMbxExtClkSpd = FREQ_25_MHZ;	/* external clock rate in MHZ */
BOOL  sysQspanPresent = TRUE;		/* PCI Bus Bridge device present? */
int   sysDramSize = MEM_SIZE_4MB;	/* On-board DRAM size */
int   sysDramSpd = MEM_SPEED_60NS;	/* On-board DRAM speed */
int   sysDimmSize = MEM_SIZE_8MB;	/* DIMM size */
int   sysFlashSize = MEM_SIZE_1MB;	/* Flash memory size */
int   sysBootType  = BOOTROM_STARTUP;	/* determines where boot takes place */
UINT  sysRamSize = DEFAULT_DRAM_SIZE;   /* total RAM size: onboard DRAM+DIMM */
UINT  sysRefClkFrq;                     /* Reference clock for CPU */

/* 
 * These globals replace the defines of the same name in mbx800.h,
 * and should be used after exiting romInit.s.
 */

int   spllMulFactor;			/* SPLL multiplic. factor in PLPRCR*/
int   spllFreq;				/* the system clock rate */
int   brgClkFreq;			/* baud rate generator clock */
int   refreshValue;			/* clock period between DRAM refresh */
int   ptaValue;				/* periodic timer A period */

#ifdef INCLUDE_ATA

/* global data structures used by the EIDE/ATA driver */

ATA_RESOURCE    ataResources[ATA_MAX_CTRLS];

/* 
 * This structure needs to be initialized for each EIDE/ATA device present
 * in the system.  It has the following layout:
 *	int cylinders;
 *	int heads;
 *	int sectorsTrack;
 *	int bytesSector;
 *	int precomp;
 */

ATA_TYPE        ataTypes [ATA_MAX_CTRLS][ATA_MAX_DRIVES] =
    {
        {
    	    { ATA_DEV0_CYL, 0, 0, 512, 0xff},  /* controller 0, drive 0 */
    	    { ATA_DEV1_CYL, 0, 0, 512, 0xff},  /* controller 0, drive 1 */
    	},
        {
    	    { ATA_DEV2_CYL, 0, 0, 512, 0xff},  /* controller 1, drive 0 */
    	    { ATA_DEV3_CYL, 0, 0, 512, 0xff},  /* controller 1, drive 1 */
    	}
    };
#endif /* INCLUDE_ATA */

#ifdef	INCLUDE_LPT

/*
 * ISA SuperIO (FDC37C67) Parallel Port (MBX Rev C) definitions.
 * On entry level boards which use the CPM PIP interface to implement
 * a parallel port, the printer driver mbxLptDrv, does not use these definitions
 * but instead automatically uses PIP definitions.
 */

LPT_RESOURCE lptResources[LPT_CHANNELS] = 
    {
        {
            C67_LPT_BASE_ADRS,	/* IO base adrs */
            C67_LPT_INT_VEC,	/* Interrupt Vector */
            C67_LPT_INT_LVL,	/* Interrupt Level */
            TRUE,		/* Enable Autofeed? */
            1000,		/* Loop count for busy wait */
            1000,		/* Loop count for strobe wait */
            10,			/* Retry count */
            1			/* Timeout (secs) for syncSem */
        },
    };

#endif	/* INCLUDE_LPT */


/* 
 * XXX set the following array to a unique Ethernet hardware address XXX
 *
 * last 5 nibbles are board specific, initialized in sysHwInit
 */

#ifdef	INCLUDE_CPM_END
unsigned char sysCpmEnetAddr [6] = {0x08, 0x00, 0x3e, 0x03, 0x02, 0x01};
#endif	/* INCLUDE_CPM_END */

/* locals */

#ifdef	INCLUDE_CPM_END
void sysCpmEnetDisable (int unit);
void sysCpmEnetIntDisable (int unit);
#endif	/* INCLUDE_CPM_END */

void sysPciTrap (ESFPPC *pEsf);

/* forward declarations */

void   		sysClkRateAdjust ( int * );
void		sysDelay( void );
void		sysMsDelay ( UINT );
void    	sysAtaInit( int, int, int );
LOCAL STATUS  	sysMbxIntConnect( VOIDFUNCPTR *, VOIDFUNCPTR, int );
LOCAL int 	sysMbxIntEnable (int);
LOCAL int 	sysMbxIntDisable (int);

/* BSP Drivers */
#ifdef INCLUDE_PCI
#include "pci/pciConfigLib.c"
#  ifdef INCLUDE_SHOW_ROUTINES
#  include "pci/pciConfigShow.c"
#  endif /* INCLUDE_SHOW_ROUTINES */ 
#endif /*INCLUDE_PCI*/

#include "sysSerial.c"
#include "intrCtl/ppc860Intr.c"
#ifdef INCLUDE_AUX_CLK
#include "timer/ppc860Timer.c"		/* PPC860 & 821 have on chip timers */
#else
#include "timer/ppcDecTimer.c"
#endif

#include "mem/byteNvRam.c"
#include "mbxI2c.c"                     /* I2C bus access */
#include "qspanPci.c"                   /* QBus-to-PCIBus bridge device */
#include "w83c553f.c"
#include "smcC67SuperIo.c"
#include "i2cMcp.c"
#include "mbxPcmcia.c"
#include "mbxLptDrv.c"

#ifdef INCLUDE_FD
#   include "fdcDrv.c"	/* include floppy disk driver */
#   include "isaDma.c"	/* include DMA driver */
#endif

/* include BSP specific WindML configuration */

#ifdef INCLUDE_WINDML
#    include "sysWindML.c"
#endif /* INCLUDE_WINDML */

/******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* RETURNS: A pointer to the string.
*/

char * sysModel (void)
    {
    return ("Motorola MBX - PowerPC 860");
    }

/******************************************************************************
*
* sysBspRev - return the bsp version with the revision eg 1.0/<x>
*
* This function returns a pointer to a bsp version with the revision.
* for eg. 1.0/<x>. BSP_REV defined in config.h is concatanated to
* BSP_VERSION and returned.
*
* RETURNS: A pointer to the BSP version/revision string.
*/

char * sysBspRev (void)
    {
    return (BSP_VERSION BSP_REV);
    }

/******************************************************************************
*
* sysClkRateAdjust - Adjust the clock frequency
*
* This function recalculates the decrementer clock frequency value
* based on the actual system clock speed.
*
* RETURNS: N/A
*/

void sysClkRateAdjust
    (
     int * sysDecClkFreq
    )
    {
    * sysDecClkFreq = sysMbxIntClkSpd / DEC_CLK_TO_INC;
    }

#ifdef INCLUDE_SYS_HW_INIT_0
/******************************************************************************
* sysHwInit0 - Used here to enable extended exception vector support.
*
* RETURNS: None.
*/ 

void sysHwInit0 () 
{
excExtendedVectors=TRUE; 
}
#endif /*INCLUDE_SYS_HW_INIT_0 */

/******************************************************************************
*
* sysHwInit - initialize the system hardware
*
* This routine initializes various feature of the MPC860ADS boards. It sets up
* the control registers, initializes various devices if they are present.
*
* NOTE: This routine should not be called directly by the user.
*
* RETURNS: N/A
*/

void sysHwInit (void)
    {
    int	immrVal = vxImmrIsbGet();
    UINT32 plprcrVal;
    int i = 0;
#ifdef INCLUDE_PCI
    UINT32	qspanAdr;	/* QSpan device registers base address */
    int         pciBusNo;       /* PCI bus number */
    int         pciDevNo;       /* PCI device number */
    int         pciFuncNo;      /* PCI function number */
    UINT32	temp;
#endif

    /* store the saved values into the global configuration vars. */

    /* Initialize DPRAM with configration parameters */