mbx800.h

vworks 下wlan的实现代码

/*
 * PCI slot definitions (BUS/DEVICE/FUNCTION - CONFADDR definition)
 * Notes:
 * 1. This version F/W does not support devices beyond BUS #0.
 * 2. These definitions are from the PC/104+ perspective.
 */

#define PCI_PCIBRIDGE	0x00009000	/* AD18 - PCIBus bridge */
#define PCI_ISABRIDGE	0x00009800	/* AD19 - ISABus bridge (F.0) */
#define PCI_EIDECTRL	0x00009900	/* AD19 - EIDE controller (F.1) */
#define PCI_SLOT1	0x0000A000	/* IDSEL0, AD20 (master/slave) */
#define PCI_SLOT2	0x0000A800	/* IDSEL1, AD21 (master/slave) */
#define PCI_SLOT3	0x0000B000	/* IDSEL2, AD22 (master/slave) */
#define PCI_SLOT4	0x0000B800	/* IDSEL3, AD23 (slave) */

/* Super I/O index/data address possibilities */

#define SIO_BASE_I_0	(CPU_PCI_ISA_IO_BA+0x398)
#define SIO_BASE_D_0	(CPU_PCI_ISA_IO_BA+0x399)
#define SIO_BASE_I_1	(CPU_PCI_ISA_IO_BA+0x26E)
#define SIO_BASE_D_1	(CPU_PCI_ISA_IO_BA+0x26F)
#define SIO_BASE_I_2	(CPU_PCI_ISA_IO_BA+0x15C)
#define SIO_BASE_D_2	(CPU_PCI_ISA_IO_BA+0x15D)
#define SIO_BASE_I_3	(CPU_PCI_ISA_IO_BA+0x02E)
#define SIO_BASE_D_3	(CPU_PCI_ISA_IO_BA+0x02F)

/* Super I/O identifier definitions (byte-wide register) */

#define NCRPC87303_ID	0x30	/* identifier for the 87303 chip */
#define NCRPC87303P_ID	0x40	/* identifier for the 87303 chip w/PHXKBBIOS */
#define NCRPC87308_ID	0xA0	/* identifier for the 87308 chip */
#define NCRPC87323_ID	0x20	/* identifier for the 87323 chip */

/* PCI device vendor/type identifier definitions */

#define PCI_NOBODYHOME          0xFFFFFFFF	/* not present */
#define PCI_ID_NCR53C810	0x00011000	/* SCSI, NCR */
#define PCI_ID_NCR53C825	0x00031000	/* SCSI, NCR */
#define PCI_ID_NCR53C875	0x000F1000	/* SCSI, NCR */
#define PCI_ID_AM79C970		0x20001022	/* Ethernet, AMD */
#define PCI_ID_DEC21040		0x00021011	/* Ethernet, DEC */
#define PCI_ID_DEC21140		0x00091011	/* Ethernet, DEC */
#define PCI_ID_GD5430		0x00A01013	/* VGA, Cirrus Logic */
#define PCI_ID_GD5434		0x00A81013	/* VGA, Cirrus Logic */
#define PCI_ID_GD5436		0x00AC1013	/* VGA, Cirrus Logic */
#define PCI_ID_GD5446		0x00B81013	/* VGA, Cirrus Logic */
#define PCI_ID_DIAMOND_PROVIPER	0x9100100E	/* VGA, Diamond */
#define PCI_ID_ATI_MACH64VT	0x56541002	/* VGA, ATI */
#define PCI_ID_MATROX_STORM	0x0519102B	/* VGA, Matrox */
#define PCI_ID_CHIPS_64310	0x00B8102C	/* VGA, CHIPS 64310 */
#define PCI_ID_SL82C105		0x010510AD	/* EIDE, Sonata (Winbond) */
#define PCI_ID_I82378		0x04848086      /* PCI-ISA Bridge, Intel */
#define PCI_ID_W83C553F		0x056510AD      /* PCI-ISA Bridge, Winbond */
#define PCI_ID_QSPAN		0x086010E3	/* QBus-PCI Bridge, Tundra */

/* programmable interrupt controller (PIC) */

#define PIC_REG_ADDR_INTERVAL	1	   /* address diff of adjacent regs. */

/* 
 * ISA Interrupt vectors
 *
 * These are additions to the default MBX8XX interrupt definitions in
 * the file ppc860Intr.h
 */

#define IV_ISA_INT0             INUM_TO_IVEC (64)       /* ISA interrupt 0 */
#define IV_ISA_INT1             INUM_TO_IVEC (65)       /* ISA interrupt 1 */
#define IV_ISA_INT2             INUM_TO_IVEC (66)       /* ISA interrupt 2 */
#define IV_ISA_INT3             INUM_TO_IVEC (67)       /* ISA interrupt 3 */
#define IV_ISA_INT4             INUM_TO_IVEC (68)       /* ISA interrupt 4 */
#define IV_ISA_INT5             INUM_TO_IVEC (69)       /* ISA interrupt 5 */
#define IV_ISA_INT6             INUM_TO_IVEC (70)       /* ISA interrupt 6 */
#define IV_ISA_INT7             INUM_TO_IVEC (71)       /* ISA interrupt 7 */
#define IV_ISA_INT8             INUM_TO_IVEC (72)       /* ISA interrupt 8 */
#define IV_ISA_INT9             INUM_TO_IVEC (73)       /* ISA interrupt 9 */
#define IV_ISA_INT10            INUM_TO_IVEC (74)       /* ISA interrupt 10 */
#define IV_ISA_INT11            INUM_TO_IVEC (75)       /* ISA interrupt 11 */
#define IV_ISA_INT12            INUM_TO_IVEC (76)       /* ISA interrupt 12 */
#define IV_ISA_INT13            INUM_TO_IVEC (77)       /* ISA interrupt 13 */
#define IV_ISA_INT14            INUM_TO_IVEC (78)       /* ISA interrupt 14 */
#define IV_ISA_INT15            INUM_TO_IVEC (79)       /* ISA interrupt 15 */

/* redefine the Maximum number of interrupts constant */

#undef	NUM_VEC_MAX
#define NUM_VEC_MAX             80

/* interrupt vector definitions */

#define INT_NUM_IRQ0		0x00	/* intr. number for IRQ0 */
#define INT_VEC_IRQ0		INT_NUM_IRQ0

/* Interrupt Vector/Number to Interrupt Level */

#define	IVEC_TO_ILVL(X)		(UINT) IVEC_TO_INUM(X)
#define	INUM_TO_ILVL(X)		(UINT) (X)

/* Interrupt Classes */

#define	INT_CLASS_PPC860	0x1
#define	INT_CLASS_RES		0x2
#define	INT_CLASS_CPM		0x3
#define	INT_CLASS_ISA_PCI	0x4
#define	INT_CLASS_UNDEF		0x5

/* Interrupt Level to Interrupt Class */

#define INT_CLASS(lev)  (lev <= 15 ? INT_CLASS_PPC860 :                        \
                         (lev <= 31 ? INT_CLASS_RES :                          \
                          (lev <= 63 ? INT_CLASS_CPM :                         \
                           (lev <= 79 ? INT_CLASS_ISA_PCI : INT_CLASS_UNDEF))))


/* defines for interrupt sources into the SIU */

#define	IV_POWERFAIL	IV_IRQ0		/* Power Fail */
#define	IV_TEMP		IV_IRQ1		/* Temp high/low */
#define	IV_QSPAN	IV_IRQ2		/* QSpan */
#define	IV_ISA_CTLR	IV_IRQ3		/* ISA Controller 1 */
#define	IV_COMINT	IV_IRQ6		/* COMMINT_L */
#define	IV_ABORT	IV_IRQ7		/* Abort or Stop */
         
#define	IV_RTC		IV_LEVEL0	/* Real-Time Clock */
#define	IV_PIT		IV_LEVEL1	/* Periodic Intr Tmr */
#define	IV_TIMEBASE	IV_LEVEL2	/* Timebase Cntr */
					/* IV_LEVEL3: Fast Ethernet Interrupt */
#define	IV_CPM_CTLR	IV_LEVEL4	/* CPM */
#define	IV_PCMCIA	IV_LEVEL5	/* PCMCIA */
#define IV_PIP		IV_LEVEL6	/* Parallel */

/* ISA interrupts for the Winbond chip */

#define IV_ISA_TIMER	IV_ISA_INT0	/* Timer */
#define IV_KEYBOARD	IV_ISA_INT1	/* Keyboard */
#define IV_COMM1	IV_ISA_INT4	/* COM Port 1 */
#define IV_COMM2	IV_ISA_INT3	/* COM Port 2 */
#define IV_FLOPPY	IV_ISA_INT6	/* Floppy */
#define IV_ISA_LPT	IV_ISA_INT7	/* Printer */
#define IV_PCI_INTA	IV_ISA_INT9	/* PCI - INTA */
#define IV_PCI_INTB	IV_ISA_INT10	/* PCI - INTB */
#define IV_PCI_INTC	IV_ISA_INT11	/* PCI - INTC */
#define IV_MOUSE        IV_ISA_INT12    /* mouse */
#define IV_PCI_INTD	IV_ISA_INT13	/* PCI - INTD */
#define IV_IDE0		IV_ISA_INT14	/* IDE 0 */
#define IV_IDE1		IV_ISA_INT15	/* IDE 1 */

/* ISA/PCI Interrupt controller definitions */

#define	IBC_INUM_BASE		0x00
#define	IBC_INUM_SYS_BASE	IVEC_TO_INUM (IV_ISA_INT0)

/* ISA UART definitions */

#define	COM1_INT_VEC		IV_COMM1
#define	COM1_BASE_ADRS		CPU_ISA_COM1_BA
#define	UART_REG_ADDR_INTERVAL	1

/* CPM UART definitions */

#define	TX_BUF_DESC_BA		0x2200
#define	RX_BUF_DESC_BA		0x2210
#define	TX_BUFFER		0x0300
#define	RX_BUFFER		0x0380

/* Port B pin definitions */

#define PORT_B_PINS_SER		((1<<7)|(1<<6)) /* serial io port B pins */
#define PORT_B_PINS_I2C		((1<<5)|(1<<4)) /* I2C port B pins */

/* ISA LPT definitions */

#define C67_LPT_BASE_ADRS	CPU_ISA_LPT1_BA
#define C67_LPT_INT_VEC		IVEC_TO_INUM (IV_ISA_LPT)
#define C67_LPT_INT_LVL		INUM_TO_ILVL (C67_LPT_INT_VEC)

/* FDC definitions */

#define	FD_BASE_ADDR		CPU_ISA_FDC_BA
#define	FD_INT_VEC		IVEC_TO_INUM (IV_FLOPPY)    /* Intr Number */
#define FD_INT_LVL		INUM_TO_ILVL (FD_INT_VEC)
#define	FD_MAX_DRIVES		4
#define FD_DMA_CHAN     	2

#ifndef _ASMLANGUAGE
#include "blkIo.h"
IMPORT STATUS fdDrv(UINT, UINT);
IMPORT BLK_DEV* fdDevCreate (UINT, UINT, UINT, UINT);
#endif

/* PCMCIA definitions */
#if (! defined (INCLUDE_WLAN_END))
#define PCMCIA_MEMORY_BA	0xE0000000	/* PCMCIA memory address */
#define PCMCIA_DMA_BA		0xE4000000	/* PCMCIA DMAO address */
#define PCMCIA_ATTRIBUTE_BA	0xE8000000	/* PCMCIA attribute address */
#define PCMCIA_IO_BA		0xEC000000	/* PCMCIA I/O address */
#define PCMCIA_MAX_SIZE		0x04000000	/* PCMCIA region sizes - 64MB */
#define PCMCIA_MAX_SOCKS	1		/* number of sockets */
#endif
#define PCMCIA_TPR		100		/* time in MS to power up */
#define PCMCIA_TPF		300		/* time in MS to power off */
#define PCMCIA_TOFF		100		/* min time for power on seq. */


/* defines for the PCI Configuration Base addresses for MEM and I/O regs. */

#define QSPAN_CFG_BA_MEM        PCI_MEM_ADRS
#define QSPAN_CTL_PCI_MEM       QSPAN_ENABLE_REG
#define QSPAN_CFG_BA_IO         (PCI_BASE_IO |                             \
                                (PCI_IO_ADRS + PCI_IO_RANGE - QSPAN_REG_SIZE))
#define QSPAN_CTL_PCI_IO        QSPAN_ENABLE_REG

/*
 * define the makeup of the QSPAN PCI Bus Target image 0
 * Base address, Translation address and Control Reg.
 */

#define QSPAN_PBTI_BA_0         PCI_SLV_MEM_BUS
#define QSPAN_PBTI_TA_0         PCI_SLV_MEM_LOCAL
#define QSPAN_PBTI_CTL_REG0     (QSPAN_QBTI_EN | PCI_SLV_MEM_CODE |         \
                                 QSPAN_QBTI_PRT_SIZ32 | QSPAN_QBTI_PWEN | \
                                 QSPAN_QBTI_MEM_SPACE)

/*
 * define the makeup of the QSPAN PCI Bus Target image 1
 * Base address, Translation address and Control Reg.
 */

#define QSPAN_PBTI_BA_1         PCI_SLV_IO_BUS
#define QSPAN_PBTI_TA_1         PCI_SLV_IO_LOCAL
#define QSPAN_PBTI_CTL_REG1     (QSPAN_DISABLE_REG | QSPAN_QBTI_IO_SPACE)

/*
 * Setup the QSPAN Slave Image 0 address translation and control registers.
 *
 * The default values are,
 *  - 32MB PCI I/O space window
 *  - mapped to PCI IO Address 0x00000000 - 0x01ffffff
 *  - no write posting
 *  - image is enabled
 */

#define QSPAN_QBSI_AT_REG0      ((PCI_MSTR_IO_BUS & 0xffff0000) |       \
                                 PCI_MSTR_IO_CODE | QSPAN_QBSI_EN)
#define QSPAN_QBSI_CTL_REG0     (QSPAN_QBSI_IO_SPACE | QSPAN_QBSI_NO_PWEN)

/*
 * Setup the QSPAN Slave Image 1 address translation and control registers.
 *
 * The default values are,
 *  - 32MB PCI MEM space window
 *  - mapped to PCI Memory Address 0x00000000 - 0x01ffffff
 *  - no write posting
 *  - image is enabled
 */

#define QSPAN_QBSI_AT_REG1      ((PCI_MSTR_MEM_BUS & 0xffff0000) |      \
                                 PCI_MSTR_MEM_CODE | QSPAN_QBSI_EN)
#define QSPAN_QBSI_CTL_REG1     (QSPAN_QBSI_MEM_SPACE | QSPAN_QBSI_NO_PWEN)


/*
 * PPC860_DPR_I2C assumes two different offsets depending on whether or not
 * the I2C/SPI microcode patch has been applied (no patch -> 0x1c80, patch
 * applied -> 0x1cc0
 *
 * The default macro is defined in drv/sio/ppc860Sio.h.
 */

#undef	PPC860_DPR_I2C
#define PPC860_DPR_I2C(dprbase)                                         \
	((VINT32 *) ((*RCCR(INTERNAL_MEM_MAP_ADDR) & 0x3) ?             \
	 (dprbase + 0x1cc0) : (dprbase + 0x1c80) ))

#define PPC860_DPR_I2C_INITIAL(dprbase) ((VINT32 *) (dprbase + 0x1c80))

#define PPC860_I2C_PATCH_INSTALLED                                      \
	((PPC860_DPR_I2C(DPRAM_ADDRESS) !=                              \
          PPC860_DPR_I2C_INITIAL(DPRAM_ADDRESS)) ? 1:0)

#ifdef __cplusplus
    }
#endif

#endif /* INCmbx800h */