mbx800.h

vworks 下wlan的实现代码

#define BCSR2_QSPAN_RESET	(1<<0)	/* reset QSpan device (write only) */
#define BCSR2_FACTORY_TEST	(1<<0)	/* factory test mode (read only) */

/* Reset BCSR1 to disable ethernet and serial */

#define BCSR1_RESET_VAL		( BCSR1_E_TP | BCSR1_E_DFD | BCSR1_RS232_DT )

/* Mask BCSR2 for LED's */

#define BCSR2_LED_MASK		( ~(BCSR2_D_PASS_FAIL_LED | \
				    BCSR2_D_STATUS_LED1 | \
				    BCSR2_D_STATUS_LED2 | \
				    BCSR2_QSPAN_RESET ) )

/* CPU type in the PVR */

#define CPU_TYPE_860			0x0050		/* value for PPC860 */
#define	CPU_REV_A1_MASK_NUM		0x0010		/* revision mask num */

/* MBX DPRAM addresses */

#define DPRAM_ADDRESS			(INTERNAL_MEM_MAP_ADDR + 0x2000)

#define MBX860_BD_SIZE                  8       /* size of 860 buffer descript*/
#define MBXI2C_NUM_BD                   2       /* buffer descriptors for I2C */
#define MBXI2C_NUM_BUFFER               32      /* buffers reserved for I2C */

#define DPRAM_I2C_OFFSET                (DPRAM_ADDRESS + 0x0500)
#define DPRAM_I2C_BD                    (DPRAM_I2C_OFFSET)
#define DPRAM_I2C_BUFFER                (DPRAM_I2C_OFFSET + \
					 (MBX860_BD_SIZE * MBXI2C_NUM_BD))

#define DPRAM_SROM_BUFFER		(DPRAM_ADDRESS + 0x0600)
#define DPRAM_SROM_BUF_SIZE		0x100

/*
 * The following are used to define space in DPRAM that is only
 * used during system bootup
 */

#define DPRAM_STACKFRM_BA	(INTERNAL_MEM_MAP_ADDR + 0x2f00)
#define DPRAM_STACK_ALLOC	-0x0020
#define DPRAM_STACK_DEALLOC	0x0020
#define DPRAM_CONFIG_PARAM_BA	(DPRAM_ADDRESS + 0x0700)
#define DPRAM_ENET_ADDR		(DPRAM_CONFIG_PARAM_BA + 0x0)
#define DPRAM_INT_CLK_SPD	(DPRAM_CONFIG_PARAM_BA + 0x08)
#define DPRAM_EXT_CLK_SPD	(DPRAM_CONFIG_PARAM_BA + 0x0C)
#define DPRAM_QSPAN_PRSNT	(DPRAM_CONFIG_PARAM_BA + 0x10)
#define DPRAM_DRAM_SIZE		(DPRAM_CONFIG_PARAM_BA + 0x14)
#define DPRAM_DRAM_SPD		(DPRAM_CONFIG_PARAM_BA + 0x18)
#define DPRAM_DIMM_SIZE		(DPRAM_CONFIG_PARAM_BA + 0x1C)
#define DPRAM_FLASH_SIZE	(DPRAM_CONFIG_PARAM_BA + 0x20)
#define DPRAM_BOOT_TYPE		(DPRAM_CONFIG_PARAM_BA + 0x24)
#define DPRAM_TOTAL_RAM_SIZE	(DPRAM_CONFIG_PARAM_BA + 0x28)
#define DPRAM_REF_CLK_FRQ	(DPRAM_CONFIG_PARAM_BA + 0x2c)

#define BASE_REG0_OFFSET	0x0100

/* SROM Identifier field values and data sizes */

#define SROM_PID_PID     0x01    /* product identifier (ASCII) */
#define SROM_SIZE_PID    0x03    /* product identifier field size */
#define SROM_PID_FAN     0x02    /* factory assembly-number (ASCII) */
#define SROM_SIZE_FAN    0x0C    /* factory assembly-number field size */
#define SROM_PID_SN      0x03    /* serial-number (ASCII) */
#define SROM_SIZE_SN     0x07    /* serial-number field size */
#define SROM_PID_PCO     0x04    /* product configuration options (binary) */
#define SROM_SIZE_PCO    0x10    /* configuration options field size */
#define SROM_PID_ICS     0x05    /* internal clock speed in HZ (integer) */
#define SROM_SIZE_ICS    0x04    /* internal clock speed field size */
#define SROM_PID_ECS     0x06    /* external clock speed in HZ (integer) */
#define SROM_SIZE_ECS    0x04    /* external clock speed field size */
#define SROM_PID_RCS     0x07    /* reference clock speed in HZ (integer) */
#define SROM_SIZE_RCS    0x04    /* reference clock speed field size */
#define SROM_PID_EA      0x08    /* ethernet address (binary) */
#define SROM_SIZE_EA     0x06    /* ethernet addr. field size */
#define SROM_PID_TERM    0xFF    /* termination value */

/* TBD - need to add a bit definition for this define */

#define SROM_QSPAN_PRSNT 0x00    /* QSPAN present bit */

/* Bit definitions for the Product Configuration Options */

#define PCO_BBRAM       0x80000000 /* battery-backed RAM (BBRAM) and socket */
#define PCO_BOOTROM	0x40000000 /* boot ROM/socket (i.e., socketed FLASH) */
#define PCO_KAPWR	0x20000000 /* keep alive power source */
#define PCO_ENET_TP	0x10000000 /* ethernet twisted pair connector (RJ45) */
#define PCO_ENET_AUI	0x08000000 /* ethernet attachment unit interface (AUI)*/
#define PCO_PCMCIA	0x04000000 /* PCMCIA socket */
#define PCO_DIMM	0x02000000 /* DIMM module socket */
#define PCO_DTT		0x01000000 /* digital thermometer and thermostat (DTT)*/
#define PCO_LCD		0x00800000 /* liquid crystal display (LCD) device */
#define PCO_PCI_DEVICE	0x00400000 /* PCI bus bridge/ ISA bridge chips */
#define PCO_PCIO_DEVS	0x00200000 /* PC I/O (COM1, COM2, FDC, LPT, Keyboard) */
#define PCO_EIDE	0x00100000 /* enhanced IDE (EIDE) header */
#define PCO_FDC		0x00080000 /* floppy disk controller (FDC) header */
#define PCO_LPT_8XX	0x00040000 /* parallel port header via MPC8xx */
#define PCO_LPT_PCIO	0x00020000 /* parallel port header via PC I/O */

#define SROM_MAX_ITEM_SIZE SROM_SIZE_PCO


/* RTC register values */
/* Key Register Unlock Value */

#define KEYED_REG_UNLOCK_VALUE		0x55CCAA33

/* defines for the default configuration values */

#define DEFAULT_CLOCK_SPEED	FREQ_25_MHZ
#define DEFAULT_DRAM_SIZE	MEM_SIZE_4MB
#define DEFAULT_DIMM_SIZE	MEM_SIZE_0MB
#define DEFAULT_FLASH_SIZE	MEM_SIZE_1MB
#define DEFAULT_BOOT_TYPE	FLASH_STARTUP
#define DEFAULT_MEM_SPEED	MEM_SPEED_60NS

/* Baud Rate Generator division factors */

#define BRG_DIV_BY_1		0
#define BRG_DIV_BY_4		1
#define BRG_DIV_BY_16		2
#define BRG_DIV_BY_64		3

#define BRGCLK_DIV_FACTOR       BRG_DIV_BY_1

/* Device configuration defines for ATA */

#define NO_DEVICE       	0	/* no device present */
#define DEV_AUTO_CONFIG 	1	/* attempt to auto-configure device */


/*
 * Primary PCI bus configuration space address and data register addresses
 * as seen by the CPU on the local bus.
 */

#define PCI_PRIMARY_CAR	(CPU_PCI_BRIDGE_BA+0x0500) /* PCI config address reg */
#define PCI_PRIMARY_CDR	(CPU_PCI_BRIDGE_BA+0x0504) /* PCI config data    reg */

/* I2C-bus device address definitions */

#define I2C_DA_DTT	0x90		/* DTT DS1621 */
#define I2C_DA_DIMM	0xA2		/* DIMM EEPROM */
#define I2C_DA_VPD	0xA4		/* VPD (vital product data) EEPROM */
#define I2C_DA_LRAM	0xA6		/* LRAM (local memory) EEPROM */

#ifndef _ASMLANGUAGE

/* PCI I/O function defines */

#ifndef PCI_IN_BYTE
#define PCI_IN_BYTE(x)          sysPciInByte (x)
#endif
IMPORT  UINT8                   sysPciInByte  (UINT32 address);
#ifndef PCI_IN_WORD
#define PCI_IN_WORD(x)          sysPciInWord (x)
#endif
IMPORT  UINT16                  sysPciInWord  (UINT32 address);
#ifndef PCI_IN_LONG
#define PCI_IN_LONG(x)          sysInLong (x)
#endif
#ifndef PCI_OUT_BYTE
#define PCI_OUT_BYTE(x,y)       sysPciOutByte (x,y)
#endif
IMPORT  void                    sysPciOutByte (UINT32 address, UINT8  data);
#ifndef PCI_OUT_WORD
#define PCI_OUT_WORD(x,y)       sysPciOutWord (x,y)
#endif
IMPORT  void                    sysPciOutWord (UINT32 address, UINT16 data);
#ifndef PCI_OUT_LONG
#define PCI_OUT_LONG(x,y)       sysOutLong (x,y)
#endif

#endif  /* _ASMLANGUAGE */

/* Cache Line Size - 32 32-bit value = 128 bytes */

#define PCI_CLINE_SZ		0x20

/* Latency Timer value - 255 PCI clocks */

#define PCI_LAT_TIMER		0xff

/*
 * The following macros define access to PCI space from the CPU,
 * and access to local DRAM from the PCI bus.  They are used in
 * conjunction with the PCI macros defined in config.h, however,
 * these macros are non-modifiable.
 */

#define PCI_MSTR_IO_BUS         0x00000000      /* must be 0 for ISA devices */
#define PCI_MSTR_SIZE_MASK	((~(PCI_MSTR_IO_SIZE) + 1) & 0xBFFF8000)

/*  There is no I/O space on the MPC bus */

#define PCI_SLV_IO_BUS         0x00000000
#define PCI_SLV_IO_LOCAL       0x00000000
#define PCI_SLV_IO_SIZE        0x00000000
#define PCI_SLV_IO_CODE        0x00000000

/* PCI/ISA I/O and Memory space definitions (from MPU's viewpoint) */

#define CPU_PCI_IO_BA           PCI_MSTR_IO_LOCAL  /* PCI I/O space base addr */
#define CPU_PCI_MEM_BA          PCI_MSTR_MEM_LOCAL /* PCI Mem space base addr */
#define CPU_PCI_ISA_IO_BA       PCI_MSTR_IO_LOCAL  /* ISA I/O space base addr */
#define CPU_PCI_ISA_MEM_BA      PCI_MSTR_MEM_LOCAL /* ISA Mem space base addr */

/* base addresses for ISA devices in ISA I/O space */

#define ISA_KBD_DATA       0x60        /* KBD STAT */
#define ISA_KBD_STATUS     0x64        /* KBD STAT */
#define ISA_IDE_CMND_BA    0x01F0      /* IDE Command regs. */
#define ISA_COM2_BA        0x02F8      /* COM2 */
#define ISA_C67_BA	   0x0370      /* SMC c67 SuperIO */
#define ISA_LPT1_BA        0x03BC      /* LPT1 */
#define ISA_FDC_BA         0x03F0      /* FDC */
#define ISA_IDE_CNTRL_BA   0x03F6      /* IDE Control regs. */
#define ISA_COM1_BA        0x03F8      /* COM1 */

/* base addresses for ISA devices as seen from CPU space */

#define CPU_ISA_KBD_DATA   (CPU_PCI_ISA_IO_BA + ISA_KBD_DATA)     /* KBD STAT */
#define CPU_ISA_KBD_STATUS (CPU_PCI_ISA_IO_BA + ISA_KBD_STATUS)   /* KBD STAT */
#define CPU_ISA_IDE_BA	   (CPU_PCI_ISA_IO_BA + ISA_IDE_CMND_BA)  /* IDE */
#define CPU_ISA_COM2_BA	   (CPU_PCI_ISA_IO_BA + ISA_COM2_BA)	  /* COM2 */
#define CPU_ISA_C67_BA	   (CPU_PCI_ISA_IO_BA + ISA_C67_BA)       /* Supr IO */
#define CPU_ISA_LPT1_BA	   (CPU_PCI_ISA_IO_BA + ISA_LPT1_BA)	  /* LPT1 */
#define CPU_ISA_FDC_BA	   (CPU_PCI_ISA_IO_BA + ISA_FDC_BA)	  /* FDC */
#define CPU_ISA_COM1_BA	   (CPU_PCI_ISA_IO_BA + ISA_COM1_BA)	  /* COM1 */

/* PCI/ISA address definitions (from PCI's viewpoint) */

#define PCI_IO_ADRS		0x01000000	/* start of PCI I/O space */
#define PCI_IO_RANGE		0x1F000000	/* size of PCI I/O space */
#define PCI_MEM_ADRS		0x01000000	/* start of PCI memory space */
#define PCI_MEM_RANGE		0x1F000000	/* size of PCI memory space */
#define ISA_IO_ADRS		0x00000000	/* start of PCI/ISA I/O space */
#define ISA_IO_RANGE		0x00800000	/* size of PCI/ISA I/O space */
#define ISA_IO_RANGE_64		0x00010000	/* size of ISA 64K I/O space */
#define ISA_MEM_ADRS		0x00000000	/* start of ISA memory space */
#define ISA_MEM_RANGE		0x01000000	/* size of ISA memory space */

/* PCI base address to access CPU local DRAM */

#define PCI2DRAM_BASE_ADRS      0x80000000     /* memory as seen from PCI bus */
#define PCI2DRAM_BASE_TRANSLATE 0x00000000

/*
 * Psuedo PREP memory map as seen from CPU
 *
 * All starting addresses are correct except for CPU_PCI_IACK_ADRS.
 * This address was selected to allow a minimum 8k memory range
 * for the MMU table entry.
 *
 * Also, the size of spaces are reduced except for CPU_PCI_IACK_ADRS.
 */

						/* base of PCI I/O space */
#define CPU_PCI_IO_ADRS		(CPU_PCI_IO_BA + PCI_IO_ADRS)
#define CPU_PCI_IO_SIZE		0x00100000	/* 1 meg */

						/* base of PCI mem space */
#define CPU_PCI_MEM_ADRS	(CPU_PCI_MEM_BA + PCI_MEM_ADRS)
#define CPU_PCI_MEM_SIZE	0x01000000	/* 16 meg */

#define CPU_PCI_IACK_ADRS	0xbfffe000	/* covers PCI IACK space */
						/* base = 0xbffffff0; */
#define CPU_PCI_IACK_SIZE	0x00002000	/* 8 kbytes */

						/* base of ISA I/O space */
#define CPU_PCI_ISA_IO_ADRS	(CPU_PCI_ISA_IO_BA + ISA_IO_ADRS)
#define CPU_PCI_ISA_IO_SIZE	0x00010000	/* 64 kbytes */

						/* base of ISA mem space */
#define CPU_PCI_ISA_MEM_ADRS	(CPU_PCI_ISA_MEM_BA + ISA_MEM_ADRS)
#define CPU_PCI_ISA_MEM_SIZE	0x00100000	/* 1 meg */

/* Allocate Device Space (Offsets) for PCI devices */

#define W83C553F_DEV_SPACE	0x10000

/* PCI view of PCI I/O Space for PCI devices */

#define PCI_IO_W83C553F_ADRS	(PCI_IO_ADRS + W83C553F_DEV_SPACE)/* Winbond */