mbx800.h

vworks 下wlan的实现代码

/* mbx800.h - Motorola MBX800 board header */

/* Copyright 1984-2001 Wind River Systems, Inc. */
/* Copyright 1997,1998,1999 Motorola, Inc., All Rights Reserved */

/*
modification history
--------------------
01r,08jul02,dtr  Adding windML support.
01q,12jun02,kab  SPR 74987: cplusplus protection
01p,16may02,dtr  Modified SYS_CPU_FREQ to read EEPROM.
01o,04mar02,dtr  Adding auxClk and timestamp capability. 
                 Removing FLASH_SIZE definition.
01n,30jan02,dtr  ATA_DEV_NONE define in ataDrv.h already, conflict because
                 used for different things..
01m,16oct01,dtr  Merge fix to SPR65678. Including mod history.
01k,09apr01,rip  changed RTC_KEY_VALUE to KEYED_REG_UNLOCK_VALUE
01l,10mar00,rcs  merge mot's latest version
01k,16nov99,rhk  added defines for PCMCIA delay times.
01j,30jun98,rhk  merged versions of WRS and MCG files.
01i,10jun98,dat  added "sysLib.h", removed conflicting prototypes.
01h,22may98,map  renamed N_SIO_CHANNELS to N_I8250_CHANNELS [SPR# 21296]
01g,29apr98,rhk  added non-configurable macros from config.h
            map  cleaned up interrupt macros
01f,12mar98,rhk  WRS code review cleanup.
01e,18nov97,rhk  moved ISA interrupt defines from ppc860Intr.h, 
		 WRS code review cleanup.
01d,27sep97,scb  Modified for crystal or 1:1 oscillator input clock.
01c,25aug97,srr  added PCI_CLINE_SZ and PCI_LAT_TIMER, from old pci.h.
                 added BBRAM_SIZE to support Validation Test Suite.
01b,05aug97,srr  inserted Aux clock defines.
01a,26jun97,srr  created from ads860, version 01e.
*/

/*
This file contains I/O addresses and related constants for the Motorola
MBX860/821 boards.
*/

#ifndef	INCmbx800h
#define	INCmbx800h

#ifdef __cplusplus
    extern "C" {
#endif

#include "drv/mem/memDev.h"
#include "drv/intrCtl/ppc860Intr.h"
#include "drv/pcmcia/pccardLib.h"
#include "drv/hdisk/ataDrv.h"
#include "mbxLptDrv.h"
#include "drv/sio/ppc860Sio.h"
#include "sysLib.h"
#include "config.h"

#define BUS	0				/* bus-less board */
#define CPU	PPC860				/* CPU type */

/* Console numbers */

#define SMC1_COM1_NUM		0

/* Board Types */

#define BOARD_TYPE_ENTRY	0
#define BOARD_TYPE_STANDARD	1

/* Serial port Types */

#define SERIAL_PORT_SMC		0
#define SERIAL_PORT_COM      	1

#if (BOARD_TYPE == BOARD_TYPE_ENTRY) && (SERIAL_PORT == SERIAL_PORT_COM)
#error "Entry level board does not support COM"
#endif

/* Number of TTYs */

#undef	NUM_TTY
#define	NUM_TTY			1

/* Number of COM (i8250) channels */

#define	N_I8250_CHANNELS	1

/* Printer Channels */

#define	LPT_CHANNELS		N_LPT_CHANNELS	/* defined in mbxLptDrv.h */

/* ATA Device config types */

#define NO_ATA_DEV		0		/* No Device attached */

#define ATA_DEV_EXISTS		1		/* Auto configure device */

/*
 * Crystal Frequency - This macro defines the input oscillator frequency
 * clocking the PPC860. On the ADS board, the CPU is clocked by a crystal
 * running at 4 Mhz.  For the MBX boards, the frequency should never change
 * from 32KHZ
 */

#define CRYSTAL_FREQ            32768           /* 32.768 Khz */

#define SYS_DELAY		50000		/* loop counter for sysDelay */

#define FREQ_20_MHZ		20000000	/* 20 Mhz */
#define FREQ_25_MHZ		25000000	/* 25 Mhz */
#define FREQ_33_MHZ		33000000	/* 33 Mhz */
#define FREQ_40_MHZ		40000000	/* 40 Mhz */
#define FREQ_50_MHZ		50000000	/* 50 Mhz */

/* 
 * MAX_MPU_SPEED used by mpc860I2cdInit(), it represents a speed which
 * can always be used for reads from I2C bus.  If we ever operate with
 * a higher CPU speed, this constant will have to be adjusted.
 */

#define MAX_MPU_SPEED           60000000

#define MEM_SIZE_0MB		0x0
#define MEM_SIZE_1MB		0x00100000
#define MEM_SIZE_2MB            0x00200000
#define MEM_SIZE_4MB            0x00400000
#define MEM_SIZE_8MB            0x00800000
#define MEM_SIZE_16MB           0x01000000
#define MEM_SIZE_32MB           0x02000000
#define MEM_SIZE_64MB           0x04000000
#define MEM_SIZE_128MB		0x08000000

#define MEM_SPEED_50NS		0x00000050
#define MEM_SPEED_60NS		0x00000060
#define MEM_SPEED_70NS		0x00000070

#define FLASH_STARTUP		0x0
#define BOOTROM_STARTUP		0x1

/* 
 * DRAM refresh frequency - This macro defines the DRAM refresh frequency.
 * i.e.: A DRAM with 1024 rows to refresh in 16ms:
 * DRAM_REFRESH_FREQ = 1024/ 16E-3 = 64E3 hz
 */

#define DRAM_REFRESH_FREQ       64000                   /* 64 kHz */

/* 
 * The dynamic bus clock speed calculation is needed,
 * so PPC_TMR_RATE_SET_ADJUST is defined here and the function
 * sysClkRateAdjust has been added to sysLib.c
 */

#define PPC_TMR_RATE_SET_ADJUST \
	(void) sysClkRateAdjust (&sysDecClkFrequency)

/*
 * SPLL Frequency - gives the SPLL frequency used in romInit.s
 * as a startup value
 */

#define SPLL_FREQ_25MHZ		0x2FB00000

/*
 * The PTP is a register used by the Memory Controller.
 * It divides the BRGCLK (Baud Rate Generator Clock) by
 * either 2, 4, 8, 16, 32 or 64 and sends this divided clock to the
 * Periodic Timers, for the UPMA and UPMB.
 */

#define PTP_VALUE	MPTPR_PTP_DIV32
#define PTP_DIVISOR	(64 / (PTP_VALUE >> 8))

/*
 * SPLL_FREQ_REQUESTED - This constant defines the expected system PLL (SPLL)
 * frequency divided by 2.
 */

#define SPLL_FREQ_REQUESTED     FREQ_25_MHZ             /* 25 Mhz */

/* define the decrementer input clock frequency */

#define DEC_CLOCK_FREQ	SPLL_FREQ_REQUESTED
#define DEC_CLK_TO_INC  16

#define SYS_CPU_FREQ     (*(UINT32 *)(DPRAM_INT_CLK_SPD))
/*
 * This macro returns the positive difference between two unsigned ints.
 * Useful for determining delta between two successive decrementer reads.
 */

#define DELTA(a,b)  ( abs((int)a - (int)b) )

/* clock rates */

#define SYS_CLK_RATE_MIN        1       /* minimum system clock rate */
#define SYS_CLK_RATE_MAX        8000    /* maximum system clock rate */

/* Aux clock rates - not supported in MBX, but included for Tornado */

#define AUX_CLK_RATE_MIN	1	/* minimum auxiliary clock rate */
#define AUX_CLK_RATE_MAX	8000	/* maximum auxiliary clock rate */

/* Internal Memory Map base Address */

#define INTERNAL_MEM_MAP_ADDR		0xFA200000	
#define INTERNAL_MEM_MAP_SIZE		0x00010000	/* 64 K bytes */

/* MPC860 Register Offsets */

#define BASE_REG0_OFFSET	0x0100

/* Memory/Device Base Addresses */

#define FLASH_P_BA		0xFE000000	/* primary flash base addr */
#define FLASH_S_BA		0xFC000000	/* secondary flash base addr */
#define FLASH_MEM_SIZE		0x00800000	/* flash size - 8 MB */
#define CPU_PCI_BRIDGE_BA	0xFA210000	/* PCI Bus Bridge base addr */
#define CPU_PCI_BRIDGE_SIZE	0x00010000	/* PCI Bus Bridge size - 64 K */
#define QSPAN_BASE_ADRS		CPU_PCI_BRIDGE_BA
#define QSPAN_IACK_REG		0x508
#define QSPAN_DEF_LAT_TIMER	0x0
#define QSPAN_DEF_CACHELINE	QSPAN_MISC0_DISABLE_CACHELINE
#define QSPAN_DEF_BUS_GRANT	QSPAN_SET_S_BG
#define QSPAN_DEF_BG_ACK	QSPAN_SET_S_BB
#define QSPAN_DEF_BYTE_ORDER	QSPAN_BOC_BE	/* use big-endian ordering */
#define QSPAN_DEF_MSTSLV_MODE	QSPAN_MSTSLV_3
#define QSPAN_REVISION_1_0	0x00000000	/* revision 1.0 ID value */
#define QSPAN_REVISION_1_1	0x00000000	/* revision 1.1 ID value */
#define QSPAN_REVISION_1_2	0x00000002	/* revision 1.2 ID value */

/* NVRAM definitions */

#define NV_RAM_BA	0xFA000000	/* NVRAM base addr */
#define NV_RAM_SIZE	0x00008000	/* 32KB default for NVRAM */
#define NV_RAM_USER_AREA 0x00002000	/* start of NVRAM user area */
#define NV_RAM_ADRS	((char *) NV_RAM_BA)
#define NV_RAM_INTRVL	1

#define BBRAM_SIZE	NV_RAM_SIZE	/* legacy for Validation Tests */

/*
 * The following is the start of user space in NVRAM, the first
 * 256 bytes are used for the boot parameter line
 */

#undef  NV_BOOT_OFFSET
#define NV_BOOT_OFFSET	NV_RAM_USER_AREA

#define FLASH_RNGS	0x00800000	/* maximum size of FLASH mem */

/* MBX board control/status register addresses */

#define	BCSR_BASE_ADDR	0xFA100000	/* BCSR base address */

#ifdef _ASMLANGUAGE
#define BCSR1		BCSR_BASE_ADDR 		/* Register 1 */
#define BCSR2		BCSR_BASE_ADDR + 0x01	/* Register 2 */
#else
#define BCSR1		((VINT8 *) (BCSR_BASE_ADDR))		/* Register 1 */
#define BCSR2		((VINT8 *) (BCSR_BASE_ADDR + 0x01))	/* Register 2 */
#endif	/* _ASMLANGUAGE */

/* MBX board control/status register definitions */

#define BCSR1_E_ET		(1<<7)	/* enable enet transceiver */
#define BCSR1_E_ETIL		(1<<6)	/* enable enet transceiver intrl lpbk */
#define BCSR1_E_EAS		(1<<5)	/* enable enet auto select (AUI/TP) */
#define BCSR1_E_TP		(1<<4)	/* set = TP, clear = AUI */
#define BCSR1_E_DFD		(1<<3)	/* disable enet full duplex mode */
#define BCSR1_E_FCOL		(1<<2)	/* force collision testing */
#define BCSR1_RS232_COM1	(1<<1)	/* set = COM1, clear = SCC1 */
#define BCSR1_RS232_DT		(1<<0)	/* disable RS232 transceiver */

#define BCSR2_PCMCIA_VCC_HZA	(0<<6)	/* PCMCIA socket VCC = High-Z */
#define BCSR2_PCMCIA_VCC_050	(1<<6)	/* PCMCIA socket VCC = +5.0V */
#define BCSR2_PCMCIA_VCC_033	(2<<6)	/* PCMCIA socket VCC = +3.3V */
#define BCSR2_PCMCIA_VCC_HZB	(3<<6)	/* PCMCIA socket VCC = High-Z */
#define BCSR2_PCMCIA_VPP_HZA	(0<<4)	/* PCMCIA socket VPP = High-Z */
#define BCSR2_PCMCIA_VPP_120	(1<<4)	/* PCMCIA socket VPP = +12.0V */
#define BCSR2_PCMCIA_VPP_VCC	(2<<4)	/* PCMCIA socket VPP = defined by VCC */
#define BCSR2_PCMCIA_VPP_HZB	(3<<4)	/* PCMCIA socket VPP = High-Z */
#define BCSR2_D_PASS_FAIL_LED	(1<<3)	/* On/Off for Pass/Fail (write only) */
#define BCSR2_BOARD_BATTERY	(1<<3)	/* board battery okay (read only) */
#define BCSR2_D_STATUS_LED1	(1<<2)	/* On/Off for Status LED2 (write only)*/
#define BCSR2_NVRAM_BATTERY	(1<<2)	/* NVRAM battery okay (read only) */
#define BCSR2_D_STATUS_LED2	(1<<1)	/* On/Off for Status LED2 (write only)*/
#define BCSR2_FLASH_STATUS	(1<<1)	/* FLASH programming stat (read only) */