📄 spwm_table.lst
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<
< // Bit set //
< .DEFINE CB_TMR4_TMRPS0 0
< .DEFINE CB_TMR4_TMRPS1 1
< .DEFINE CB_TMR4_TMRPS2 2
< .DEFINE CB_TMR4_CKEGS0 3
< .DEFINE CB_TMR4_CKEGS1 4
< .DEFINE CB_TMR4_CCLS0 5
< .DEFINE CB_TMR4_CCLS1 6
< .DEFINE CB_TMR4_CCLS2 7
< .DEFINE CB_TMR4_MODE0 10
< .DEFINE CB_TMR4_MODE1 11
< .DEFINE CB_TMR4_MODE2 12
< .DEFINE CB_TMR4_MODE3 13
< .DEFINE CB_TMR4_PRDINT0 14
< .DEFINE CB_TMR4_PRDINT1 15
<
< // P_TMR0_IOCtrl register //
< // word set //
< .DEFINE CW_TMR0_IOAMOD_Output_00 0x0000
< .DEFINE CW_TMR0_IOAMOD_Output_01 0x0001
< .DEFINE CW_TMR0_IOAMOD_Output_10 0x0002
< .DEFINE CW_TMR0_IOAMOD_Output_11 0x0003
< .DEFINE CW_TMR0_IOAMOD_Output_Hold 0x0004
< .DEFINE CW_TMR0_IOAMOD_Capture_Rising 0x0008
< .DEFINE CW_TMR0_IOAMOD_Capture_Falling 0x0009
< .DEFINE CW_TMR0_IOAMOD_Capture_Both 0x000A
< .DEFINE CW_TMR0_IOAMOD_Capture_PDR 0x000C
< .DEFINE CW_TMR0_IOBMOD_Output_00 (0x0000 << 4)
< .DEFINE CW_TMR0_IOBMOD_Output_01 (0x0001 << 4)
< .DEFINE CW_TMR0_IOBMOD_Output_10 (0x0002 << 4)
< .DEFINE CW_TMR0_IOBMOD_Output_11 (0x0003 << 4)
< .DEFINE CW_TMR0_IOBMOD_Output_Hold (0x0004 << 4)
< .DEFINE CW_TMR0_IOBMOD_Capture_Rising (0x0008 << 4)
< .DEFINE CW_TMR0_IOBMOD_Capture_Falling (0x0009 << 4)
< .DEFINE CW_TMR0_IOBMOD_Capture_Both (0x000A << 4)
< .DEFINE CW_TMR0_IOBMOD_Capture_PDR (0x000C << 4)
< .DEFINE CW_TMR0_IOCMOD_Output_00 (0x0000 << 8)
< .DEFINE CW_TMR0_IOCMOD_Output_01 (0x0001 << 8)
< .DEFINE CW_TMR0_IOCMOD_Output_10 (0x0002 << 8)
< .DEFINE CW_TMR0_IOCMOD_Output_11 (0x0003 << 8)
< .DEFINE CW_TMR0_IOCMOD_Output_Hold (0x0004 << 8)
< .DEFINE CW_TMR0_IOCMOD_Capture_Rising (0x0008 << 8)
< .DEFINE CW_TMR0_IOCMOD_Capture_Falling (0x0009 << 8)
< .DEFINE CW_TMR0_IOCMOD_Capture_Both (0x000A << 8)
< .DEFINE CW_TMR0_IOCMOD_Capture_PDR (0x000C << 8)
<
< // Bit set //
< .DEFINE CB_TMR0_IOAMOD0 0
< .DEFINE CB_TMR0_IOAMOD1 1
< .DEFINE CB_TMR0_IOAMOD2 2
< .DEFINE CB_TMR0_IOAMOD3 3
< .DEFINE CB_TMR0_IOBMOD0 4
< .DEFINE CB_TMR0_IOBMOD1 5
< .DEFINE CB_TMR0_IOBMOD2 6
< .DEFINE CB_TMR0_IOBMOD3 7
< .DEFINE CB_TMR0_IOCMOD0 8
< .DEFINE CB_TMR0_IOCMOD1 9
< .DEFINE CB_TMR0_IOCMOD2 10
< .DEFINE CB_TMR0_IOCMOD3 11
<
< // P_TMR1_IOCtrl register //
< // word set //
< .DEFINE CW_TMR1_IOAMOD_Output_00 0x0000
< .DEFINE CW_TMR1_IOAMOD_Output_01 0x0001
< .DEFINE CW_TMR1_IOAMOD_Output_10 0x0002
< .DEFINE CW_TMR1_IOAMOD_Output_11 0x0003
< .DEFINE CW_TMR1_IOAMOD_Output_Hold 0x0004
< .DEFINE CW_TMR1_IOAMOD_Capture_Rising 0x0008
< .DEFINE CW_TMR1_IOAMOD_Capture_Falling 0x0009
< .DEFINE CW_TMR1_IOAMOD_Capture_Both 0x000A
< .DEFINE CW_TMR1_IOAMOD_Capture_PDR 0x000C
< .DEFINE CW_TMR1_IOBMOD_Output_00 (0x0000 << 4)
< .DEFINE CW_TMR1_IOBMOD_Output_01 (0x0001 << 4)
< .DEFINE CW_TMR1_IOBMOD_Output_10 (0x0002 << 4)
< .DEFINE CW_TMR1_IOBMOD_Output_11 (0x0003 << 4)
< .DEFINE CW_TMR1_IOBMOD_Output_Hold (0x0004 << 4)
< .DEFINE CW_TMR1_IOBMOD_Capture_Rising (0x0008 << 4)
< .DEFINE CW_TMR1_IOBMOD_Capture_Falling (0x0009 << 4)
< .DEFINE CW_TMR1_IOBMOD_Capture_Both (0x000A << 4)
< .DEFINE CW_TMR1_IOBMOD_Capture_PDR (0x000C << 4)
< .DEFINE CW_TMR1_IOCMOD_Output_00 (0x0000 << 8)
< .DEFINE CW_TMR1_IOCMOD_Output_01 (0x0001 << 8)
< .DEFINE CW_TMR1_IOCMOD_Output_10 (0x0002 << 8)
< .DEFINE CW_TMR1_IOCMOD_Output_11 (0x0003 << 8)
< .DEFINE CW_TMR1_IOCMOD_Output_Hold (0x0004 << 8)
< .DEFINE CW_TMR1_IOCMOD_Capture_Rising (0x0008 << 8)
< .DEFINE CW_TMR1_IOCMOD_Capture_Falling (0x0009 << 8)
< .DEFINE CW_TMR1_IOCMOD_Capture_Both (0x000A << 8)
< .DEFINE CW_TMR1_IOCMOD_Capture_PDR (0x000C << 8)
<
< // Bit set //
< .DEFINE CB_TMR1_IOAMOD0 0
< .DEFINE CB_TMR1_IOAMOD1 1
< .DEFINE CB_TMR1_IOAMOD2 2
< .DEFINE CB_TMR1_IOAMOD3 3
< .DEFINE CB_TMR1_IOBMOD0 4
< .DEFINE CB_TMR1_IOBMOD1 5
< .DEFINE CB_TMR1_IOBMOD2 6
< .DEFINE CB_TMR1_IOBMOD3 7
< .DEFINE CB_TMR1_IOCMOD0 8
< .DEFINE CB_TMR1_IOCMOD1 9
< .DEFINE CB_TMR1_IOCMOD2 10
< .DEFINE CB_TMR1_IOCMOD3 11
<
< // P_TMR2_IOCtrl register //
< // word set //
< .DEFINE CW_TMR2_IOAMOD_Output_00 0x0000
< .DEFINE CW_TMR2_IOAMOD_Output_01 0x0001
< .DEFINE CW_TMR2_IOAMOD_Output_10 0x0002
< .DEFINE CW_TMR2_IOAMOD_Output_11 0x0003
< .DEFINE CW_TMR2_IOAMOD_Output_Hold 0x0004
< .DEFINE CW_TMR2_IOAMOD_Capture_Rising 0x0008
< .DEFINE CW_TMR2_IOAMOD_Capture_Falling 0x0009
< .DEFINE CW_TMR2_IOAMOD_Capture_Both 0x000A
< .DEFINE CW_TMR2_IOBMOD_Output_00 (0x0000 << 4)
< .DEFINE CW_TMR2_IOBMOD_Output_01 (0x0001 << 4)
< .DEFINE CW_TMR2_IOBMOD_Output_10 (0x0002 << 4)
< .DEFINE CW_TMR2_IOBMOD_Output_11 (0x0003 << 4)
< .DEFINE CW_TMR2_IOBMOD_Output_Hold (0x0004 << 4)
< .DEFINE CW_TMR2_IOBMOD_Capture_Rising (0x0008 << 4)
< .DEFINE CW_TMR2_IOBMOD_Capture_Falling (0x0009 << 4)
< .DEFINE CW_TMR2_IOBMOD_Capture_Both (0x000A << 4)
<
< // Bit set //
< .DEFINE CB_TMR2_IOAMOD0 0
< .DEFINE CB_TMR2_IOAMOD1 1
< .DEFINE CB_TMR2_IOAMOD2 2
< .DEFINE CB_TMR2_IOAMOD3 3
< .DEFINE CB_TMR2_IOBMOD0 4
< .DEFINE CB_TMR2_IOBMOD1 5
< .DEFINE CB_TMR2_IOBMOD2 6
< .DEFINE CB_TMR2_IOBMOD3 7
<
< // P_TMR3_IOCtrl register //
< // word set //
< .DEFINE CW_TMR3_IOAMOD_Output_00 0x0000
< .DEFINE CW_TMR3_IOAMOD_Output_01 0x0001
< .DEFINE CW_TMR3_IOAMOD_Output_10 0x0002
< .DEFINE CW_TMR3_IOAMOD_Output_11 0x0003
< .DEFINE CW_TMR3_IOAMOD_Output_Hold 0x0004
< .DEFINE CW_TMR3_IOBMOD_Output_00 (0x0000 << 4)
< .DEFINE CW_TMR3_IOBMOD_Output_01 (0x0001 << 4)
< .DEFINE CW_TMR3_IOBMOD_Output_10 (0x0002 << 4)
< .DEFINE CW_TMR3_IOBMOD_Output_11 (0x0003 << 4)
< .DEFINE CW_TMR3_IOBMOD_Output_Hold (0x0004 << 4)
< .DEFINE CW_TMR3_IOCMOD_Output_00 (0x0000 << 8)
< .DEFINE CW_TMR3_IOCMOD_Output_01 (0x0001 << 8)
< .DEFINE CW_TMR3_IOCMOD_Output_10 (0x0002 << 8)
< .DEFINE CW_TMR3_IOCMOD_Output_11 (0x0003 << 8)
< .DEFINE CW_TMR3_IOCMOD_Output_Hold (0x0004 << 8)
<
< // Bit set //
< .DEFINE CB_TMR3_IOAMOD0 0
< .DEFINE CB_TMR3_IOAMOD1 1
< .DEFINE CB_TMR3_IOAMOD2 2
< .DEFINE CB_TMR3_IOAMOD3 3
< .DEFINE CB_TMR3_IOBMOD0 4
< .DEFINE CB_TMR3_IOBMOD1 5
< .DEFINE CB_TMR3_IOBMOD2 6
< .DEFINE CB_TMR3_IOBMOD3 7
< .DEFINE CB_TMR3_IOCMOD0 8
< .DEFINE CB_TMR3_IOCMOD1 9
< .DEFINE CB_TMR3_IOCMOD2 10
< .DEFINE CB_TMR3_IOCMOD3 11
<
< // P_TMR4_IOCtrl register //
< // word set //
< .DEFINE CW_TMR4_IOAMOD_Output_00 0x0000
< .DEFINE CW_TMR4_IOAMOD_Output_01 0x0001
< .DEFINE CW_TMR4_IOAMOD_Output_10 0x0002
< .DEFINE CW_TMR4_IOAMOD_Output_11 0x0003
< .DEFINE CW_TMR4_IOAMOD_Output_Hold 0x0004
< .DEFINE CW_TMR4_IOBMOD_Output_00 (0x0000 << 4)
< .DEFINE CW_TMR4_IOBMOD_Output_01 (0x0001 << 4)
< .DEFINE CW_TMR4_IOBMOD_Output_10 (0x0002 << 4)
< .DEFINE CW_TMR4_IOBMOD_Output_11 (0x0003 << 4)
< .DEFINE CW_TMR4_IOBMOD_Output_Hold (0x0004 << 4)
< .DEFINE CW_TMR4_IOCMOD_Output_00 (0x0000 << 8)
< .DEFINE CW_TMR4_IOCMOD_Output_01 (0x0001 << 8)
< .DEFINE CW_TMR4_IOCMOD_Output_10 (0x0002 << 8)
< .DEFINE CW_TMR4_IOCMOD_Output_11 (0x0003 << 8)
< .DEFINE CW_TMR4_IOCMOD_Output_Hold (0x0004 << 8)
<
< // Bit set //
< .DEFINE CB_TMR4_IOAMOD0 0
< .DEFINE CB_TMR4_IOAMOD1 1
< .DEFINE CB_TMR4_IOAMOD2 2
< .DEFINE CB_TMR4_IOAMOD3 3
< .DEFINE CB_TMR4_IOBMOD0 4
< .DEFINE CB_TMR4_IOBMOD1 5
< .DEFINE CB_TMR4_⌨️ 快捷键说明
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