📄 spwm_table.lst
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< .DEFINE CW_TMR0_SPCK_FCKdiv1 (0x0000 << 14)
< .DEFINE CW_TMR0_SPCK_FCKdiv2 (0x0001 << 14)
< .DEFINE CW_TMR0_SPCK_FCKdiv4 (0x0002 << 14)
< .DEFINE CW_TMR0_SPCK_FCKdiv8 (0x0003 << 14)
<
< // Bit set //
< .DEFINE CB_TMR0_TMRPS0 0
< .DEFINE CB_TMR0_TMRPS1 1
< .DEFINE CB_TMR0_TMRPS2 2
< .DEFINE CB_TMR0_CKEGS0 3
< .DEFINE CB_TMR0_CKEGS1 4
< .DEFINE CB_TMR0_CCLS0 5
< .DEFINE CB_TMR0_CCLS1 6
< .DEFINE CB_TMR0_CCLS2 7
< .DEFINE CB_TMR0_CLEGS0 8
< .DEFINE CB_TMR0_CLEGS1 9
< .DEFINE CB_TMR0_MODE0 10
< .DEFINE CB_TMR0_MODE1 11
< .DEFINE CB_TMR0_MODE2 12
< .DEFINE CB_TMR0_MODE3 13
< .DEFINE CB_TMR0_SPCK0 14
< .DEFINE CB_TMR0_SPCK1 15
<
< // P_TMR1_Ctrl register //
< // word set //
< .DEFINE CW_TMR1_TMRPS_FCKdiv1 0x0000
< .DEFINE CW_TMR1_TMRPS_FCKdiv4 0x0001
< .DEFINE CW_TMR1_TMRPS_FCKdiv16 0x0002
< .DEFINE CW_TMR1_TMRPS_FCKdiv64 0x0003
< .DEFINE CW_TMR1_TMRPS_FCKdiv256 0x0004
< .DEFINE CW_TMR1_TMRPS_FCKdiv1024 0x0005
< .DEFINE CW_TMR1_TMRPS_TCLKA 0x0006
< .DEFINE CW_TMR1_TMRPS_TCLKB 0x0007
< .DEFINE CW_TMR1_CKEGS_Rising (0x0000 << 3)
< .DEFINE CW_TMR1_CKEGS_Falling (0x0001 << 3)
< .DEFINE CW_TMR1_CKEGS_Both (0x0002 << 3)
< .DEFINE CW_TMR1_CCLS_Disabled (0x0000 << 5)
< .DEFINE CW_TMR1_CCLS_TGRA (0x0001 << 5)
< .DEFINE CW_TMR1_CCLS_TGRB (0x0002 << 5)
< .DEFINE CW_TMR1_CCLS_TGRC (0x0003 << 5)
< .DEFINE CW_TMR1_CCLS_PDR6 (0x0004 << 5)
< .DEFINE CW_TMR1_CCLS_PDR3 (0x0005 << 5)
< .DEFINE CW_TMR1_CCLS_PDR (0x0006 << 5)
< .DEFINE CW_TMR1_CCLS_TPR (0x0007 << 5)
< .DEFINE CW_TMR1_CLEGS_NotClear (0x0000 << 8)
< .DEFINE CW_TMR1_CLEGS_Rising (0x0001 << 8)
< .DEFINE CW_TMR1_CLEGS_Falling (0x0002 << 8)
< .DEFINE CW_TMR1_CLEGS_Both (0x0003 << 8)
< .DEFINE CW_TMR1_MODE_Normal (0x0000 << 10)
< .DEFINE CW_TMR1_MODE_Mode1 (0x0004 << 10)
< .DEFINE CW_TMR1_MODE_Mode2 (0x0005 << 10)
< .DEFINE CW_TMR1_MODE_Mode3 (0x0006 << 10)
< .DEFINE CW_TMR1_MODE_Mode4 (0x0007 << 10)
< .DEFINE CW_TMR1_MODE_PWM_Edge (0x0008 << 10)
< .DEFINE CW_TMR1_MODE_PWM_Center (0x000A << 10)
< .DEFINE CW_TMR1_SPCK_FCKdiv1 (0x0000 << 14)
< .DEFINE CW_TMR1_SPCK_FCKdiv2 (0x0001 << 14)
< .DEFINE CW_TMR1_SPCK_FCKdiv4 (0x0002 << 14)
< .DEFINE CW_TMR1_SPCK_FCKdiv8 (0x0003 << 14)
<
< // Bit set //
< .DEFINE CB_TMR1_TMRPS0 0
< .DEFINE CB_TMR1_TMRPS1 1
< .DEFINE CB_TMR1_TMRPS2 2
< .DEFINE CB_TMR1_CKEGS0 3
< .DEFINE CB_TMR1_CKEGS1 4
< .DEFINE CB_TMR1_CCLS0 5
< .DEFINE CB_TMR1_CCLS1 6
< .DEFINE CB_TMR1_CCLS2 7
< .DEFINE CB_TMR1_CLEGS0 8
< .DEFINE CB_TMR1_CLEGS1 9
< .DEFINE CB_TMR1_MODE0 10
< .DEFINE CB_TMR1_MODE1 11
< .DEFINE CB_TMR1_MODE2 12
< .DEFINE CB_TMR1_MODE3 13
< .DEFINE CB_TMR1_SPCK0 14
< .DEFINE CB_TMR1_SPCK1 15
<
< // P_TMR2_Ctrl register //
< // word set //
< .DEFINE CW_TMR2_TMRPS_FCKdiv1 0x0000
< .DEFINE CW_TMR2_TMRPS_FCKdiv4 0x0001
< .DEFINE CW_TMR2_TMRPS_FCKdiv16 0x0002
< .DEFINE CW_TMR2_TMRPS_FCKdiv64 0x0003
< .DEFINE CW_TMR2_TMRPS_FCKdiv256 0x0004
< .DEFINE CW_TMR2_TMRPS_FCKdiv1024 0x0005
< .DEFINE CW_TMR2_TMRPS_TCLKA 0x0006
< .DEFINE CW_TMR2_TMRPS_TCLKB 0x0007
< .DEFINE CW_TMR2_CKEGS_Rising (0x0000 << 3)
< .DEFINE CW_TMR2_CKEGS_Falling (0x0001 << 3)
< .DEFINE CW_TMR2_CKEGS_Both (0x0002 << 3)
< .DEFINE CW_TMR2_CCLS_Disabled (0x0000 << 5)
< .DEFINE CW_TMR2_CCLS_TGRA (0x0001 << 5)
< .DEFINE CW_TMR2_CCLS_TGRB (0x0002 << 5)
< .DEFINE CW_TMR2_CCLS_TPR (0x0007 << 5)
< .DEFINE CW_TMR2_CLEGS_NotClear (0x0000 << 8)
< .DEFINE CW_TMR2_CLEGS_Rising (0x0001 << 8)
< .DEFINE CW_TMR2_CLEGS_Falling (0x0002 << 8)
< .DEFINE CW_TMR2_CLEGS_Both (0x0003 << 8)
< .DEFINE CW_TMR2_MODE_Normal (0x0000 << 10)
< .DEFINE CW_TMR2_MODE_PWM_Edge (0x0008 << 10)
< .DEFINE CW_TMR2_MODE_PWM_Center (0x000A << 10)
< .DEFINE CW_TMR2_SPCK_FCKdiv1 (0x0000 << 14)
< .DEFINE CW_TMR2_SPCK_FCKdiv2 (0x0001 << 14)
< .DEFINE CW_TMR2_SPCK_FCKdiv4 (0x0002 << 14)
< .DEFINE CW_TMR2_SPCK_FCKdiv8 (0x0003 << 14)
<
< // Bit set //
< .DEFINE CB_TMR2_TMRPS0 0
< .DEFINE CB_TMR2_TMRPS1 1
< .DEFINE CB_TMR2_TMRPS2 2
< .DEFINE CB_TMR2_CKEGS0 3
< .DEFINE CB_TMR2_CKEGS1 4
< .DEFINE CB_TMR2_CCLS0 5
< .DEFINE CB_TMR2_CCLS1 6
< .DEFINE CB_TMR2_CCLS2 7
< .DEFINE CB_TMR2_CLEGS0 8
< .DEFINE CB_TMR2_CLEGS1 9
< .DEFINE CB_TMR2_MODE0 10
< .DEFINE CB_TMR2_MODE1 11
< .DEFINE CB_TMR2_MODE2 12
< .DEFINE CB_TMR2_MODE3 13
< .DEFINE CB_TMR2_SPCK0 14
< .DEFINE CB_TMR2_SPCK1 15
<
< // P_TMR3_Ctrl register //
< // word set //
< .DEFINE CW_TMR3_TMRPS_FCKdiv1 0x0000
< .DEFINE CW_TMR3_TMRPS_FCKdiv4 0x0001
< .DEFINE CW_TMR3_TMRPS_FCKdiv16 0x0002
< .DEFINE CW_TMR3_TMRPS_FCKdiv64 0x0003
< .DEFINE CW_TMR3_TMRPS_FCKdiv256 0x0004
< .DEFINE CW_TMR3_TMRPS_FCKdiv1024 0x0005
< .DEFINE CW_TMR3_TMRPS_TCLKA 0x0006
< .DEFINE CW_TMR3_TMRPS_TCLKB 0x0007
< .DEFINE CW_TMR3_CKEGS_Rising (0x0000 << 3)
< .DEFINE CW_TMR3_CKEGS_Falling (0x0001 << 3)
< .DEFINE CW_TMR3_CKEGS_Both (0x0002 << 3)
< .DEFINE CW_TMR3_CCLS_Disabled (0x0000 << 5)
< .DEFINE CW_TMR3_CCLS_TPR (0x0007 << 5)
<
< //.DEFINE CW_TMR3_LDOK (0x0001 << 9)
<
< .DEFINE CW_TMR3_MODE_Normal (0x0000 << 10)
< .DEFINE CW_TMR3_MODE_PWM_Edge (0x0008 << 10)
< .DEFINE CW_TMR3_MODE_PWM_Center (0x000A << 10)
< .DEFINE CW_TMR3_PRDINT_Period (0x0000 << 14)
< .DEFINE CW_TMR3_PRDINT_2Period (0x0001 << 14)
< .DEFINE CW_TMR3_PRDINT_4Period (0x0002 << 14)
< .DEFINE CW_TMR3_PRDINT_8Period (0x0003 << 14)
<
< // Bit set //
< .DEFINE CB_TMR3_TMRPS0 0
< .DEFINE CB_TMR3_TMRPS1 1
< .DEFINE CB_TMR3_TMRPS2 2
< .DEFINE CB_TMR3_CKEGS0 3
< .DEFINE CB_TMR3_CKEGS1 4
< .DEFINE CB_TMR3_CCLS0 5
< .DEFINE CB_TMR3_CCLS1 6
< .DEFINE CB_TMR3_CCLS2 7
< .DEFINE CB_TMR3_MODE0 10
< .DEFINE CB_TMR3_MODE1 11
< .DEFINE CB_TMR3_MODE2 12
< .DEFINE CB_TMR3_MODE3 13
< .DEFINE CB_TMR3_PRDINT0 14
< .DEFINE CB_TMR3_PRDINT1 15
<
< // P_TMR4_Ctrl register //
< // word set //
< .DEFINE CW_TMR4_TMRPS_FCKdiv1 0x0000
< .DEFINE CW_TMR4_TMRPS_FCKdiv4 0x0001
< .DEFINE CW_TMR4_TMRPS_FCKdiv16 0x0002
< .DEFINE CW_TMR4_TMRPS_FCKdiv64 0x0003
< .DEFINE CW_TMR4_TMRPS_FCKdiv256 0x0004
< .DEFINE CW_TMR4_TMRPS_FCKdiv1024 0x0005
< .DEFINE CW_TMR4_TMRPS_TCLKA 0x0006
< .DEFINE CW_TMR4_TMRPS_TCLKB 0x0007
< .DEFINE CW_TMR4_CKEGS_Rising (0x0000 << 3)
< .DEFINE CW_TMR4_CKEGS_Falling (0x0001 << 3)
< .DEFINE CW_TMR4_CKEGS_Both (0x0002 << 3)
< .DEFINE CW_TMR4_CCLS_Disabled (0x0000 << 5)
< .DEFINE CW_TMR4_CCLS_TPR (0x0007 << 5)
<
< //.DEFINE CW_TMR4_LDOK (0x0001 << 9)
<
< .DEFINE CW_TMR4_MODE_Normal (0x0000 << 10)
< .DEFINE CW_TMR4_MODE_PWM_Edge (0x0008 << 10)
< .DEFINE CW_TMR4_MODE_PWM_Center (0x000A << 10)
< .DEFINE CW_TMR4_PRDINT_Period (0x0000 << 14)
< .DEFINE CW_TMR4_PRDINT_2Period (0x0001 << 14)
< .DEFINE CW_TMR4_PRDINT_4Period (0x0002 << 14)
< .DEFINE CW_TMR4_PRDINT_8Period (0x0003 << 14)
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