📄 spwm_table.lst
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< // E. Standard Peripheral Interface SPI register //
< //***************************************************************************//
< //***************************************************************************//
< .DEFINE P_SPI_Ctrl 0x7140
< .DEFINE P_SPI_TxStatus 0x7141
< .DEFINE P_SPI_TxBuf 0x7142
< .DEFINE P_SPI_RxStatus 0x7143
< .DEFINE P_SPI_RxBuf 0x7144
<
< //***************************************************************************//
< //***************************************************************************//
< // F. Flash organization and control register //
< //***************************************************************************//
< //***************************************************************************//
< .DEFINE P_Flash_RW 0x7554
< .DEFINE P_Flash_Cmd 0x7555
<
< //***************************************************************************//
< //***************************************************************************//
< // G. UART Control Register //
< //***************************************************************************//
< //***************************************************************************//
< .DEFINE P_UART_Data 0x7100
< .DEFINE P_UART_RXStatus 0x7101
< .DEFINE P_UART_Ctrl 0x7102
< .DEFINE P_UART_BaudRate 0x7103
< .DEFINE P_UART_Status 0x7104
<
< //***************************************************************************//
< //***************************************************************************//
< // H. Compare Match Timer Register //
< //***************************************************************************//
< //***************************************************************************//
< .DEFINE P_CMT_Start 0x7500
< .DEFINE P_CMT_Ctrl 0x7501
< .DEFINE P_CMT0_TCNT 0x7508
< .DEFINE P_CMT1_TCNT 0x7509
< .DEFINE P_CMT0_TPR 0x7510
< .DEFINE P_CMT1_TPR 0x7511
<
< //***************************************************************************//
< //***************************************************************************//
< // I. Time Base Register //
< //***************************************************************************//
< //***************************************************************************//
< .DEFINE P_TMB_Reset 0x70B8
< .DEFINE P_BZO_Ctrl 0x70B9
<
< //***************************************************************************//
< //***************************************************************************//
< //Constant Definition //
< //***************************************************************************//
< //***************************************************************************//
< //=================================//
< // Generic Port register //
< //=================================//
< // bit set //
< .DEFINE CB_BIT0 0
< .DEFINE CB_BIT1 1
< .DEFINE CB_BIT2 2
< .DEFINE CB_BIT3 3
< .DEFINE CB_BIT4 4
< .DEFINE CB_BIT5 5
< .DEFINE CB_BIT6 6
< .DEFINE CB_BIT7 7
< .DEFINE CB_BIT8 8
< .DEFINE CB_BIT9 9
< .DEFINE CB_BIT10 10
< .DEFINE CB_BIT11 11
< .DEFINE CB_BIT12 12
< .DEFINE CB_BIT13 13
< .DEFINE CB_BIT14 14
< .DEFINE CB_BIT15 15
<
< //=================================//
< // flash control register //
< //=================================//
<
< // P_Wait_Enter register //
< // word set //
< .DEFINE CW_WaitCMD 0x5005
< .DEFINE CW_WaitClr 0x0001
<
< // P_Stdby_Enter register //
< // word set //
< .DEFINE CW_StdbyCMD 0xA00A
< .DEFINE CW_StdbyClr 0x0001
<
< // P_System_Option register //
< // word set //
< .DEFINE CW_SYS_CLK_R 0x0000
< .DEFINE CW_SYS_CLK_OSC 0x0001
< .DEFINE CW_SYS_WDG_Disable (0x0000 << 1)
< .DEFINE CW_SYS_WDG_Enable (0x0001 << 1)
< .DEFINE CW_SYS_LVR_Disable (0x0000 << 2)
< .DEFINE CW_SYS_LVR_Enable (0x0001 << 2)
< .DEFINE CW_SYS_LVD_Disable (0x0000 << 3)
< .DEFINE CW_SYS_LVD_Enable (0x0001 << 3)
< .DEFINE CW_SYS_Security_Protect (0x0000 << 4)
< .DEFINE CW_SYS_Security_NoProtect (0x0001 << 4)
< .DEFINE CW_SYS_Verification (0x02AA << 5)
<
< // Bit set //
< .DEFINE CB_SYS_CLK 0
< .DEFINE CB_SYS_WDG 1
< .DEFINE CB_SYS_LVR 2
< .DEFINE CB_SYS_LVD 3
< .DEFINE CB_SYS_Security 4
< .DEFINE CB_SYS_Verification0 5
< .DEFINE CB_SYS_Verification1 6
< .DEFINE CB_SYS_Verification2 7
< .DEFINE CB_SYS_Verification3 8
< .DEFINE CB_SYS_Verification4 9
< .DEFINE CB_SYS_Verification5 10
< .DEFINE CB_SYS_Verification6 11
< .DEFINE CB_SYS_Verification7 12
< .DEFINE CB_SYS_Verification8 13
< .DEFINE CB_SYS_Verification9 14
< .DEFINE CB_SYS_Verification10 15
<
< // P_Reset_Status register //
< // word set //
< .DEFINE CW_CLEAR_EXTRF 0x0001
< .DEFINE CW_CLEAR_PORF (0x0001 << 1)
< .DEFINE CW_CLEAR_WDRF (0x0001 << 2)
< .DEFINE CW_CLEAR_LPLVRF (0x0001 << 3)
< .DEFINE CW_CLEAR_SPLVRF (0x0001 << 4)
< .DEFINE CW_CLEAR_IARF (0x0001 << 5)
< .DEFINE CW_CLEAR_IIRF (0x0001 << 6)
< .DEFINE CW_CLEAR_FCHK (0x0055 << 9)
<
< // Bit set //
< .DEFINE CB_CLEAR_EXTRF 0
< .DEFINE CB_CLEAR_PORF 1
< .DEFINE CB_CLEAR_WDRF 2
< .DEFINE CB_CLEAR_LVRF 3
< .DEFINE CB_CLEAR_IARF 5
< .DEFINE CB_CLEAR_IIRF 6
< .DEFINE CB_CLEAR_FCHK0 8
< .DEFINE CB_CLEAR_FCHK1 9
< .DEFINE CB_CLEAR_FCHK2 10
< .DEFINE CB_CLEAR_FCHK3 11
< .DEFINE CB_CLEAR_FCHK4 12
< .DEFINE CB_CLEAR_FCHK5 13
< .DEFINE CB_CLEAR_FCHK6 14
< .DEFINE CB_CLEAR_FCHK7 15
<
< // P_Clk_Ctrl register //
< // word set //
< .DEFINE CW_CLK_OSCIE (0x0001 << 14)
< .DEFINE CW_CLK_OSCSF (0x0001 << 15)
<
< // Bit set //
< .DEFINE CB_CLK_OSCIE 14
< .DEFINE CB_CLK_OSCSF 15
<
< // P_WatchDog_Ctrl register //
< // word set //
< .DEFINE CW_WDPS_FCKdiv65536 0x0000
< .DEFINE CW_WDPS_FCKdiv32768 0x0001
< .DEFINE CW_WDPS_FCKdiv16384 0x0002
< .DEFINE CW_WDPS_FCKdiv8192 0x0003
< .DEFINE CW_WDPS_FCKdiv4096 0x0004
< .DEFINE CW_WDPS_FCKdiv2048 0x0005
< .DEFINE CW_WDPS_FCKdiv1024 0x0006
< .DEFINE CW_WDPS_FCKdiv512 0x0007
<
< .DEFINE CW_WDCHK_Setting (0x0015 << 3)
< .DEFINE CW_WDRS_SYS_Reset (0x0000 << 14)
< .DEFINE CW_WDRS_CPU_Reset (0x0001 << 14)
< .DEFINE CW_WDEN (0x0001 << 15)
< .DEFINE CW_WatchDog_Clear 0xA005
<
< // Bit set //
< .DEFINE CB_WDPS0 0
< .DEFINE CB_WDPS1 1
< .DEFINE CB_WDPS2 2
< .DEFINE CB_WDCHK0 3
< .DEFINE CB_WDCHK1 4
< .DEFINE CB_WDCHK2 5
< .DEFINE CB_WDCHK3 6
< .DEFINE CB_WDCHK4 7
< .DEFINE CB_WDRS 14
< .DEFINE CB_WDEN 15
<
< // P_Wakeup_Ctrl register //
< // word set //
< .DEFINE CW_CMTWE_Enable (0x0001<<4)
< .DEFINE CW_PDC0WE_Enable (0x0001<<5)
< .DEFINE CW_PDC1WE_Enable (0x0001<<6)
< .DEFINE CW_TPM2WE_Enable (0x0001<<7)
< .DEFINE CW_EXT0WE_Enable (0x0001<<11)
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