📄 spwm_table.lst
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Sunplus u'nSP Assembler - Ver. 1.14.3.1
Listing File Has Been Relocated
.INCLUDE Spmc75_regs.inc
< // =========================================================================
< // The information contained herein is the exclusive property of
< // Sunplus Technology Co. And shall not be distributed, reproduced,
< // or disclosed in whole in part without prior written permission.
< // (C) COPYRIGHT 2001 SUNPLUS TECHNOLOGY CO.
< // ALL RIGHTS RESERVED
< // The entire notice above must be reproduced on all authorized copies.
< // =========================================================================
< // File Name : spmc75_regs.inc
< // Description : SPMC75F2413A register definition
< // Processor : SPMC75X series
< // Author : Chih ming Huang
< // Tools : u'nSP IDE tools v1.18.1A or later version
< // Version : 1.00
< // Security : Confidential Proprietary
< // E-Mail : MaxHuang@sunplus.com.tw
< // =========================================================================
<
< //***************************************************************************//
< //***************************************************************************//
< // A. CPU control register //
< //***************************************************************************//
< //***************************************************************************//
< .DEFINE P_System_Option 0x8000
< .DEFINE P_Wait_Enter 0x700C
< .DEFINE P_Stdby_Enter 0x700E
< .DEFINE P_Reset_Status 0x7006
< .DEFINE P_Clk_Ctrl 0x7007
< .DEFINE P_WatchDog_Ctrl 0x700A
< .DEFINE P_WatchDog_Clr 0x700B
< .DEFINE P_Wakeup_Ctrl 0x700F
< .DEFINE P_INT_Status 0x70A0
< .DEFINE P_INT_Priority 0x70A4
< .DEFINE P_MisINT_Ctrl 0x70A8
<
< //***************************************************************************//
< //***************************************************************************//
< // B. I/O Port register //
< //***************************************************************************//
< //***************************************************************************//
< .DEFINE P_IOA_Data 0x7060
< .DEFINE P_IOA_Buffer 0x7061
< .DEFINE P_IOA_Dir 0x7062
< .DEFINE P_IOA_Attrib 0x7063
< .DEFINE P_IOA_Latch 0x7064
< .DEFINE P_IOA_SPE 0x7080
< .DEFINE P_IOA_KCER 0x7084
<
< .DEFINE P_IOB_Data 0x7068
< .DEFINE P_IOB_Buffer 0x7069
< .DEFINE P_IOB_Dir 0x706A
< .DEFINE P_IOB_Attrib 0x706B
< .DEFINE P_IOB_Latch 0x706C
< .DEFINE P_IOB_SPE 0x7081
<
< .DEFINE P_IOC_Data 0x7070
< .DEFINE P_IOC_Buffer 0x7071
< .DEFINE P_IOC_Dir 0x7072
< .DEFINE P_IOC_Attrib 0x7073
< .DEFINE P_IOC_Latch 0x7074
< .DEFINE P_IOC_SPE 0x7082
<
< .DEFINE P_IOD_Data 0x7078
< .DEFINE P_IOD_Buffer 0x7079
< .DEFINE P_IOD_Dir 0x707A
< .DEFINE P_IOD_Attrib 0x707B
< .DEFINE P_IOD_Latch 0x707C
<
< //***************************************************************************//
< //***************************************************************************//
< // C. Timer 0,Timer 1,Timer 2,Timer 3,Timer 4 //
< //***************************************************************************//
< //***************************************************************************//
< .DEFINE P_TMR0_Ctrl 0x7400
< .DEFINE P_TMR1_Ctrl 0x7401
< .DEFINE P_TMR2_Ctrl 0x7402
< .DEFINE P_TMR3_Ctrl 0x7403
< .DEFINE P_TMR4_Ctrl 0x7404
<
< .DEFINE P_TMR_LDOK 0x740A
<
< .DEFINE P_TMR0_TCNT 0x7430
< .DEFINE P_TMR1_TCNT 0x7431
< .DEFINE P_TMR2_TCNT 0x7432
< .DEFINE P_TMR3_TCNT 0x7433
< .DEFINE P_TMR4_TCNT 0x7434
<
< .DEFINE P_TMR0_TGRA 0x7440
< .DEFINE P_TMR0_TGRB 0x7441
< .DEFINE P_TMR0_TGRC 0x7442
<
< .DEFINE P_TMR1_TGRA 0x7443
< .DEFINE P_TMR1_TGRB 0x7444
< .DEFINE P_TMR1_TGRC 0x7445
<
< .DEFINE P_TMR2_TGRA 0x7446
< .DEFINE P_TMR2_TGRB 0x7447
<
< .DEFINE P_TMR3_TGRA 0x7448
< .DEFINE P_TMR3_TGRB 0x7449
< .DEFINE P_TMR3_TGRC 0x744A
< .DEFINE P_TMR3_TGRD 0x744B
<
< .DEFINE P_TMR4_TGRA 0x744C
< .DEFINE P_TMR4_TGRB 0x744D
< .DEFINE P_TMR4_TGRC 0x744E
< .DEFINE P_TMR4_TGRD 0x744F
<
< .DEFINE P_TMR0_TPR 0x7435
< .DEFINE P_TMR1_TPR 0x7436
< .DEFINE P_TMR2_TPR 0x7437
< .DEFINE P_TMR3_TPR 0x7438
< .DEFINE P_TMR4_TPR 0x7439
<
< .DEFINE P_TMR0_TBRA 0x7450
< .DEFINE P_TMR0_TBRB 0x7451
< .DEFINE P_TMR0_TBRC 0x7452
<
< .DEFINE P_TMR1_TBRA 0x7453
< .DEFINE P_TMR1_TBRB 0x7454
< .DEFINE P_TMR1_TBRC 0x7455
<
< .DEFINE P_TMR2_TBRA 0x7456
< .DEFINE P_TMR2_TBRB 0x7457
<
< .DEFINE P_TMR3_TBRA 0x7458
< .DEFINE P_TMR3_TBRB 0x7459
< .DEFINE P_TMR3_TBRC 0x745A
<
< .DEFINE P_TMR4_TBRA 0x745C
< .DEFINE P_TMR4_TBRB 0x745D
< .DEFINE P_TMR4_TBRC 0x745E
<
< .DEFINE P_TMR0_IOCtrl 0x7410
< .DEFINE P_TMR1_IOCtrl 0x7411
< .DEFINE P_TMR2_IOCtrl 0x7412
< .DEFINE P_TMR3_IOCtrl 0x7413
< .DEFINE P_TMR4_IOCtrl 0x7414
<
< .DEFINE P_TMR0_INT 0x7420
< .DEFINE P_TMR1_INT 0x7421
< .DEFINE P_TMR2_INT 0x7422
< .DEFINE P_TMR3_INT 0x7423
< .DEFINE P_TMR4_INT 0x7424
<
< .DEFINE P_TMR0_Status 0x7425
< .DEFINE P_TMR1_Status 0x7426
< .DEFINE P_TMR2_Status 0x7427
< .DEFINE P_TMR3_Status 0x7428
< .DEFINE P_TMR4_Status 0x7429
<
< .DEFINE P_TMR_Start 0x7405
< .DEFINE P_TMR_Output 0x7406
<
< .DEFINE P_TMR3_OutputCtrl 0x7407
< .DEFINE P_TMR4_OutputCtrl 0x7408
<
< .DEFINE P_POS0_DectCtrl 0x7462
< .DEFINE P_POS1_DectCtrl 0x7463
<
< .DEFINE P_POS0_DectData 0x7464
< .DEFINE P_POS1_DectData 0x7465
<
< .DEFINE P_TMR3_DeadTime 0x7460
< .DEFINE P_TMR4_DeadTime 0x7461
<
< .DEFINE P_TPWM_Write 0x7409
<
< .DEFINE P_Fault1_Ctrl 0x7466
< .DEFINE P_Fault2_Ctrl 0x7467
<
< .DEFINE P_OL1_Ctrl 0x7468
< .DEFINE P_OL2_Ctrl 0x7469
<
< .DEFINE P_Fault1_Release 0x746A
< .DEFINE P_Fault2_Release 0x746B
<
< //***************************************************************************//
< //***************************************************************************//
< // D. 10-bit ADC converter register //
< //***************************************************************************//
< //***************************************************************************//
< .DEFINE P_ADC_Setup 0x7160
< .DEFINE P_ADC_Ctrl 0x7161
< .DEFINE P_ADC_Data 0x7162
< .DEFINE P_ADC_Channel 0x7166
<
< //***************************************************************************//
< //***************************************************************************//
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