2407reg.h

用于dsp2407a的普通i/o口的测试

EVAIMRC         .set 742Eh ; Group C Interrupt Mask Register
EVAIFRA         .set 742Fh ; Group A Interrupt Flag Register
EVAIFRB         .set 7430h ; Group B Interrupt Flag Register
EVAIFRC         .set 7431h ; Group C Interrupt Flag Register

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; Event Manager B (EVB) registers
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GPTCONB         .set 7500h ; GP Timer control register B
T3CNT           .set 7501h ; GP Timer 3 counter register
T3CMPR          .set 7502h ; GP Timer 3 compare register
T3PR            .set 7503h ; GP Timer 3 period register
T3CON           .set 7504h ; GP Timer 3 control register
T4CNT           .set 7505h ; GP Timer 4 counter register
T4CMPR          .set 7506h ; GP Timer 4 compare register
T4PR            .set 7507h ; GP Timer 4 period register
T4CON           .set 7508h ; GP Timer 4 control register
COMCONB         .set 7511h ; Compare control register B
ACTRB           .set 7513h ; Full compare Action control register B
DBTCONB         .set 7515h ; Dead-band timer control register B
CMPR4           .set 7517h ; Full compare unit compare register4
CMPR5           .set 7518h ; Full compare unit compare register5
CMPR6           .set 7519h ; Full compare unit compare register6
CAPCONB         .set 7520h ; Capture control register B
CAPFIFOB        .set 7522h ; Capture FIFO status register B
CAP4FIFO        .set 7523h ; Capture Channel 4 FIFO Top
CAP5FIFO        .set 7524h ; Capture Channel 5 FIFO Top
CAP6FIFO        .set 7525h ; Capture Channel 6 FIFO Top
CAP4FBOT        .set 7527h ; Bottom reg. of capture FIFO stack 4
CAP5FBOT        .set 7527h ; Bottom reg. of capture FIFO stack 5
CAP6FBOT        .set 7527h ; Bottom reg. of capture FIFO stack 6
EVBIMRA         .set 752Ch ; Group A Interrupt Mask Register
EVBIMRB         .set 752Dh ; Group B Interrupt Mask Register
EVBIMRC         .set 752Eh ; Group C Interrupt Mask Register
EVBIFRA         .set 752Fh ; Group A Interrupt Flag Register
EVBIFRB         .set 7530h ; Group B Interrupt Flag Register
EVBIFRC         .set 7531h ; Group C Interrupt Flag Register


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; CAN registers
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CANMDER         .set 7100h ; CAN Mailbox Direction/Enable register
CANTCR          .set 7101h ; CAN Transmission Control register
CANRCR          .set 7102h ; CAN Recieve Control register
CANMCR          .set 7103h ; CAN Master Control register
CANBCR2         .set 7104h ; CAN Bit Config register 2
CANBCR1         .set 7105h ; CAN Bit Config register 1
CANESR          .set 7106h ; CAN Error Status register
CANGSR          .set 7107h ; CAN Global Status register
CANCEC          .set 7108h ; CAN Trans and Rcv Err counters
CANIFR          .set 7109h ; CAN Interrupt Flag Register
CANIMR          .set 710ah ; CAN Interrupt Mask Register
CANLAM0H        .set 710bh ; CAN Local Acceptance Mask MBX0/1
CANLAM0L        .set 710ch ; CAN Local Acceptance Mask MBX0/1
CANLAM1H        .set 710dh ; CAN Local Acceptance Mask MBX2/3
CANLAM1L        .set 710eh ; CAN Local Acceptance Mask MBX2/3
CANMSGID0L      .set 7200h ; CAN Message ID for mailbox 0 (lower 16 bits)
CANMSGID0H      .set 7201h ; CAN Message ID for mailbox 0 (upper 16 bits)
CANMSGCTRL0     .set 7202h ; CAN RTR and DLC
CANMBX0A        .set 7204h ; CAN 2 of 8 bytes of Mailbox 0
CANMBX0B        .set 7205h ; CAN 2 of 8 bytes of Mailbox 0
CANMBX0C        .set 7206h ; CAN 2 of 8 bytes of Mailbox 0
CANMBX0D        .set 7207h ; CAN 2 of 8 bytes of Mailbox 0
CANMSGID1L      .set 7208h ; CAN Message ID for mailbox 1 (lower 16 bits)
CANMSGID1H      .set 7209h ; CAN Message ID for mailbox 1 (upper 16 bits)
CANMSGCTRL1     .set 720Ah ; CAN RTR and DLC
CANMBX1A        .set 720Ch ; CAN 2 of 8 bytes of Mailbox 1
CANMBX1B        .set 720Dh ; CAN 2 of 8 bytes of Mailbox 1
CANMBX1C        .set 720Eh ; CAN 2 of 8 bytes of Mailbox 1
CANMBX1D        .set 720Fh ; CAN 2 of 8 bytes of Mailbox 1
CANMSGID2L      .set 7210h ; CAN Message ID for mailbox 2 (lower 16 bits)
CANMSGID2H      .set 7211h ; CAN Message ID for mailbox 2 (upper 16 bits)
CANMSGCTRL2     .set 7212h ; CAN RTR and DLC
CANMBX2A        .set 7214h ; CAN 2 of 8 bytes of Mailbox 2
CANMBX2B        .set 7215h ; CAN 2 of 8 bytes of Mailbox 2
CANMBX2C        .set 7216h ; CAN 2 of 8 bytes of Mailbox 2
CANMBX2D        .set 7217h ; CAN 2 of 8 bytes of Mailbox 2
CANMSGID3L      .set 7218h ; CAN Message ID for mailbox 3 (lower 16 bits)
CANMSGID3H      .set 7219h ; CAN Message ID for mailbox 3 (upper 16 bits)
CANMSGCTRL3     .set 721Ah ; CAN RTR and DLC
CANMBX3A        .set 721Ch ; CAN 2 of 8 bytes of Mailbox 3
CANMBX3B        .set 721Dh ; CAN 2 of 8 bytes of Mailbox 3
CANMBX3C        .set 721Eh ; CAN 2 of 8 bytes of Mailbox 3
CANMBX3D        .set 721Fh ; CAN 2 of 8 bytes of Mailbox 3
CANMSGID4L      .set 7220h ; CAN Message ID for mailbox 4 (lower 16 bits)
CANMSGID4H      .set 7221h ; CAN Message ID for mailbox 4 (upper 16 bits)
CANMSGCTRL4     .set 7222h ; CAN RTR and DLC
CANMBX4A        .set 7224h ; CAN 2 of 8 bytes of Mailbox 4
CANMBX4B        .set 7225h ; CAN 2 of 8 bytes of Mailbox 4
CANMBX4C        .set 7226h ; CAN 2 of 8 bytes of Mailbox 4
CANMBX4D        .set 7227h ; CAN 2 of 8 bytes of Mailbox 4
CANMSGID5L      .set 7228h ; CAN Message ID for mailbox 5 (lower 16 bits)
CANMSGID5H      .set 7229h ; CAN Message ID for mailbox 5 (upper 16 bits)
CANMSGCTRL5     .set 722Ah ; CAN RTR and DLC
CANMBX5A        .set 722Ch ; CAN 2 of 8 bytes of Mailbox 5
CANMBX5B        .set 722Dh ; CAN 2 of 8 bytes of Mailbox 5
CANMBX5C        .set 722Eh ; CAN 2 of 8 bytes of Mailbox 5
CANMBX5D        .set 722Fh ; CAN 2 of 8 bytes of Mailbox 5
; Code security module (CSM) registers (Data memory)
KEY3            .set 77F0h ; High word of the 64-bit KEY register
KEY2            .set 77F1h ; Third word of the 64-bit KEY register
KEY1            .set 77F2h ; Second word of the 64-bit KEY register
KEY0            .set 77F3h ; Low word of the 64-bit KEY register
; Code security module (CSM) registers (Program memory)
PWL3            .set 0040h ; High word of the 64–bit password
PWL2            .set 0041h ; Third word of the 64–bit password
PWL1            .set 0042h ; Second word of the 64–bit password
PWL0            .set 0043h ; Low word of the 64–bit password


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; I/O space mapped registers
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WSGR            .set 0FFFFh ; Wait-State Generator Control register
FCMR            .set 0FF0Fh ; Flash control mode register


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; Bit codes for Test bit instruction (BIT) (15 Loads bit 0 into TC)
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BIT15           .set 0000h ; Bit Code for 15
BIT14           .set 0001h ; Bit Code for 14
BIT13           .set 0002h ; Bit Code for 13
BIT12           .set 0003h ; Bit Code for 12
BIT11           .set 0004h ; Bit Code for 11
BIT10           .set 0005h ; Bit Code for 10
BIT9            .set 0006h ; Bit Code for 9
BIT8            .set 0007h ; Bit Code for 8
BIT7            .set 0008h ; Bit Code for 7
BIT6            .set 0009h ; Bit Code for 6
BIT5            .set 000Ah ; Bit Code for 5
BIT4            .set 000Bh ; Bit Code for 4
BIT3            .set 000Ch ; Bit Code for 3
BIT2            .set 000Dh ; Bit Code for 2
BIT1            .set 000Eh ; Bit Code for 1     
BIT0            .set 000Fh ; Bit Code for 0