📄 2407reg.h
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; File name: 2407reg.h
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; Description: 2407 register definitions, Bit codes for BIT instruction
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; 240x CPU core registers
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IMR .set 0004h ; Interrupt Mask Register
IFR .set 0006h ; Interrupt Flag Register
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; System configuration and interrupt registers
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SCSR1 .set 7018h ; System Control & Status register. 1
SCSR2 .set 7019h ; System Control & Status register. 2
DINR .set 701Ch ; Device Identification Number register.
PIVR .set 701Eh ; Peripheral Interrupt Vector register.
PIRQR0 .set 7010h ; Peripheral Interrupt Request register 0
PIRQR1 .set 7011h ; Peripheral Interrupt Request register 1
PIRQR2 .set 7012h ; Peripheral Interrupt Request register 2
PIACKR0 .set 7014h ; Peripheral Interrupt Acknowledge register 0
PIACKR1 .set 7015h ; Peripheral Interrupt Acknowledge register 1
PIACKR2 .set 7016h ; Peripheral Interrupt Acknowledge register 2
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; External interrupt configuration registers
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XINT1CR .set 7070h ; External interrupt 1 control register
XINT2CR .set 7071h ; External interrupt 2 control register
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; Digital I/O registers
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MCRA .set 7090h ; I/O Mux Control Register A
MCRB .set 7092h ; I/O Mux Control Register B
MCRC .set 7094h ; I/O Mux Control Register C
PADATDIR .set 7098h ; I/O port A Data & Direction register
PBDATDIR .set 709Ah ; I/O port B Data & Direction register
PCDATDIR .set 709Ch ; I/O port C Data & Direction register
PDDATDIR .set 709Eh ; I/O port D Data & Direction register
PEDATDIR .set 7095h ; I/O port E Data & Direction register
PFDATDIR .set 7096h ; I/O port F Data & Direction register
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; Watchdog (WD) registers
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WDCNTR .set 7023h ; WD Counter register
WDKEY .set 7025h ; WD Key register
WDCR .set 7029h ; WD Control register
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; ADC registers
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ADCTRL1 .set 70A0h ; ADC Control register 1
ADCTRL2 .set 70A1h ; ADC Control register 2
MAXCONV .set 70A2h ; Maximum conversion channels register
CHSELSEQ1 .set 70A3h ; Channel select Sequencing control register 1
CHSELSEQ2 .set 70A4h ; Channel select Sequencing control register 2
CHSELSEQ3 .set 70A5h ; Channel select Sequencing control register 3
CHSELSEQ4 .set 70A6h ; Channel select Sequencing control register 4
AUTO_SEQ_SR .set 70A7h ; Auto–sequence status register
RESULT0 .set 70A8h ; Conversion result register 0
RESULT1 .set 70A9h ; Conversion result register 1
RESULT2 .set 70Aah ; Conversion result register 2
RESULT3 .set 70Abh ; Conversion result register 3
RESULT4 .set 70Ach ; Conversion result register 4
RESULT5 .set 70Adh ; Conversion result register 5
RESULT6 .set 70Aeh ; Conversion result register 6
RESULT7 .set 70Afh ; Conversion result register 7
RESULT8 .set 70B0h ; Conversion result register 8
RESULT9 .set 70B1h ; Conversion result register 9
RESULT10 .set 70B2h ; Conversion result register 10
RESULT11 .set 70B3h ; Conversion result register 11
RESULT12 .set 70B4h ; Conversion result register 12
RESULT13 .set 70B5h ; Conversion result register 13
RESULT14 .set 70B6h ; Conversion result register 14
RESULT15 .set 70B7h ; Conversion result register 15
CALIBRATION .set 70B8h ; Calibration result, used to correct
; subsequent conversions
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; SPI registers
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SPICCR .set 7040h ; SPI Config Control register
SPICTL .set 7041h ; SPI Operation Control register
SPISTS .set 7042h ; SPI Status register
SPIBRR .set 7044h ; SPI Baud rate control register
SPIRXEMU .set 7046h ; SPI Emulation buffer register
SPIRXBUF .set 7047h ; SPI Serial receive buffer register
SPITXBUF .set 7048h ; SPI Serial transmit buffer register
SPIDAT .set 7049h ; SPI Serial data register
SPIPRI .set 704Fh ; SPI Priority control register
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; SCI registers
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SCICCR .set 7050h ; SCI Communication control register
SCICTL1 .set 7051h ; SCI Control register 1
SCIHBAUD .set 7052h ; SCI Baud Rate MS byte register
SCILBAUD .set 7053h ; SCI Baud Rate LS byte register
SCICTL2 .set 7054h ; SCI Control register 2
SCIRXST .set 7055h ; SCI Receiver Status register
SCIRXEMU .set 7056h ; SCI Emulation Data Buffer register
SCIRXBUF .set 7057h ; SCI Receiver Data buffer register
SCITXBUF .set 7059h ; SCI Transmit Data buffer register
SCIPRI .set 705Fh ; SCI Priority control register
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; Event Manager A (EVA) registers
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GPTCONA .set 7400h ; GP Timer control register A
T1CNT .set 7401h ; GP Timer 1 counter register
T1CMPR .set 7402h ; GP Timer 1 compare register
T1PR .set 7403h ; GP Timer 1 period register
T1CON .set 7404h ; GP Timer 1 control register
T2CNT .set 7405h ; GP Timer 2 counter register
T2CMPR .set 7406h ; GP Timer 2 compare register
T2PR .set 7407h ; GP Timer 2 period register
T2CON .set 7408h ; GP Timer 2 control register
COMCONA .set 7411h ; Compare control register A
ACTRA .set 7413h ; Full compare Action control register A
DBTCONA .set 7415h ; Dead-band timer control register A
CMPR1 .set 7417h ; Full compare unit compare register1
CMPR2 .set 7418h ; Full compare unit compare register2
CMPR3 .set 7419h ; Full compare unit compare register3
CAPCONA .set 7420h ; Capture control register A
CAPFIFOA .set 7422h ; Capture FIFO status register A
CAP1FIFO .set 7423h ; Capture Channel 1 FIFO Top
CAP2FIFO .set 7424h ; Capture Channel 2 FIFO Top
CAP3FIFO .set 7425h ; Capture Channel 3 FIFO Top
CAP1FBOT .set 7427h ; Bottom reg. of capture FIFO stack 1
CAP2FBOT .set 7428h ; Bottom reg. of capture FIFO stack 2
CAP3FBOT .set 7429h ; Bottom reg. of capture FIFO stack 3
EVAIMRA .set 742Ch ; Group A Interrupt Mask Register
EVAIMRB .set 742Dh ; Group B Interrupt Mask Register
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