2440zlg7290.searchresults

arm9 s3c2440与zlg7290的接口程序。在 ADS1.2下通过编译并能运行。

---- Pclk Matches (14 in 4 files) ----
2440init.s:	; Setting value Fclk:Hclk:Pclk
Option.inc:;(4) Select Clock Division (Fclk:Hclk:Pclk)
Userlib.c:// Hclk = Fclk/Hclk_Ratio, Pclk = Fclk/Hclk_Ratio/Pclk_Ratio.
Userlib.c:U32 Mdiv, Pdiv, Sdiv, Fclk, Hclk, Pclk, Hdivn, Pdivn, Hclk_Ratio, Pclk_Ratio, Ref_Cnt;
Userlib.c:// Hclk = Fclk/Hclk_Ratio, Pclk = Fclk/Hclk_Ratio/Pclk_Ratio.
Userlib.c:	// Calc Fclk, Hclk, Pclk
Userlib.c:	Pclk = (U32)( (((float)Fclk/(float)Hclk_Ratio)/(float)Pclk_Ratio));
Userlib.c:	Uart_Init(Pclk, 115200);
Userlib.c:		//Uart_Printf("%4.3f:%4.3f:%4.3f MHz]\n", (float)Fclk/MEGA, (float)Hclk/MEGA, (float)Pclk/MEGA);
Userlib.c:		Uart_Printf("%4.1f:%4.1f:%4.1f MHz]\n", (float)Fclk/MEGA, (float)Hclk/MEGA, (float)Pclk/MEGA);
Userlib.c:    rWTCON = ((Pclk/1000000-1)<<8)|(divider<<3);  //Watch-dog timer control register
Userlib.c:    rWTCON = ((Pclk/1000000-1)<<8);
Xmain.c:extern U32 Mdiv, Pdiv, Sdiv, Fclk, Hclk, Pclk, Hdivn, Pdivn, Hclk_Ratio, Pclk_Ratio, Ref_Cnt;
Xmain.c:	Uart_Init(Pclk, 115200);