swmii.h

vt6528芯片交换机API函数和文档运行程序

/*
 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
 * All rights reserved.
 *
 * This software is copyrighted by and is the sole property of
 * VIA Networking Technologies, Inc. This software may only be used
 * in accordance with the corresponding license agreement. Any unauthorized
 * use, duplication, transmission, distribution, or disclosure of this
 * software is expressly forbidden.
 *
 * This software is provided by VIA Networking Technologies, Inc. "as is"
 * and any express or implied warranties, including, but not limited to, the
 * implied warranties of merchantability and fitness for a particular purpose
 * are disclaimed. In no event shall VIA Networking Technologies, Inc.
 * be liable for any direct, indirect, incidental, special, exemplary, or
 * consequential damages.
 *
 *
 * File:    swmii.h
 *
 * Purpose: Phy register hardware accessing functions
 *
 * Author:  Tevin Chen
 *
 * Date:    Jan 08, 2002
 *
 */


#ifndef __SWMII_H__
#define __SWMII_H__

#if !defined(__TTYPE_H__)
#include "ttype.h"
#endif




/*---------------------  Export Definitions  ------------------------*/
//
// Common registers in MII (register offset unit is UINT16)
//
#define MII_REG_BMCR            0x00        // Basic Mode Control Register
#define MII_REG_BMSR            0x01        // Basic Mode Status Register
#define MII_REG_PHYID1          0x02        // PHY Identifier Register #1: OUI
#define MII_REG_PHYID2          0x03        // PHY Identifier Register #2: OUI + Module ID + REV ID
#define MII_REG_ANAR            0x04        // Auto-negotiation Advertisement Register
#define MII_REG_ANLPAR          0x05        // Auto-negotiation Link Partner Ability Register
#define MII_REG_ANER            0x06        // Auto-negotiation Expansion Register
#define MII_REG_NPTR            0x07        // Next Page Transmit Register
#define MII_REG_LPNPR           0x08        // Link Partner Next Page Register
#define MII_REG_GBTCR           0x09        // 1000BASE-T Control Register
#define MII_REG_GBTSR           0x0A        // 1000BASE-T Status Register

// Proprietary registers of vendors
#define MII_REG_MARVELL_PSCR    0x10        // Phy Specific Control Register
#define MII_REG_VIA_NWAYFRC     0x19        // VIA Nway-Force Register
#define MII_REG_CICADA_ACSR     0x1C        // CICADA ACSR Register




//
// Bits in the BMCR register (00h)
//
#define BMCR_SPD1           0x0040  //
#define BMCR_COL            0x0080  // Collision Test Enable
#define BMCR_FDX            0x0100  // Duplex Mode
#define BMCR_REAUTO         0x0200  // Restart Auto-Negotiation
#define BMCR_ISO            0x0400  // Isolate
#define BMCR_PD             0x0800  // Power-Down
#define BMCR_AUTO           0x1000  // Auto-Negotiation Enable
#define BMCR_SPD0           0x2000  // SPD1 SPD0  ForcedSpeed
                                    //   0    0   10Mbps
                                    //   0    1   100Mbps
                                    //   1    0   1000Mbps
                                    //   1    1   Reserved
#define BMCR_LBK            0x4000  // Lookback
#define BMCR_RESET          0x8000  // Software reset


//
// Bits in the BMSR register (01h)
//
#define BMSR_EXTCA          0x0001  // Extended Capability
#define BMSR_JAB            0x0002  // Jabber Detect
#define BMSR_LINK           0x0004  // Link Status
#define BMSR_AUTOCA         0x0008  // Auto-Negotiation Capability
#define BMSR_RF             0x0010  // Remote Fault
#define BMSR_AUTOCM         0x0020  // Auto-Negotiation Complete
#define BMSR_PREAMBLE       0x0040  // Preamble Suppression Capability
#define BMSR_EXTST          0x0100  // Extended Status Enable
#define BMSR_100T2H         0x0200  // 100BASE-T2 HDX Capability
#define BMSR_100T2F         0x0400  // 100BASE-T2 FDX Capability
#define BMSR_10TH           0x0800  // 10BASE-T HDX Capability
#define BMSR_10TF           0x1000  // 10BASE-T FDX Capability
#define BMSR_100XH          0x2000  // 100BASE-X HDX Capability
#define BMSR_100XF          0x4000  // 100BASE-X FDX Capability
#define BMSR_100T4          0x8000  // 100BASE-T4 Capability


//
// Bits in the PHYID2 register (03h)
//
#define PHYID2_MOD_ID_MSK   0xFFF0  // module id mask
#define PHYID2_REV_ID_MSK   0x000F  // revision id mask


//
// Bits in the ANAR register (04h)
//
#define ANAR_10TXH          0x0020  // Advertise 10BASE-T HDX
#define ANAR_10TXF          0x0040  // Advertise 10BASE-T FDX
#define ANAR_100TXH         0x0080  // Advertise 100BASE-X HDX
#define ANAR_100TXF         0x0100  // Advertise 100BASE-X FDX
#define ANAR_T4             0x0200  // Advertise 100BASE-T4 Capability
#define ANAR_PAUSE          0x0400  // Advertise Symmetric PAUSE Capability
#define ANAR_ASMDIR         0x0800  // Advertise Asymmetric PAUSE Capability
#define ANAR_RF             0x2000  // Transmit Remote Fault
#define ANAR_NEXT           0x8000  // Next-Page Transmission Request
#define ANAR_ABL_MEGA       (ANAR_100TXF | ANAR_100TXH | ANAR_10TXF | ANAR_10TXH)


//
// Bits in the ANLPAR register (05h)
//
#define ANLPAR_10TXH        0x0020  // LP Advertise 10BASE-T HDX
#define ANLPAR_10TXF        0x0040  // LP Advertise 10BASE-T FDX
#define ANLPAR_100TXH       0x0080  // LP Advertise 100BASE-X HDX
#define ANLPAR_100TXF       0x0100  // LP Advertise 100BASE-X FDX
#define ANLPAR_T4           0x0200  // LP Advertise 100BASE-T4 Capability
#define ANLPAR_PAUSE        0x0400  // LP Symmetric PAUSE Capability
#define ANLPAR_ASMDIR       0x0800  // LP Asymmetric PAUSE Capability
#define ANLPAR_RF           0x2000  // LP Remote Fault
#define ANLPAR_ACK          0x4000  // LP Acknowledge
#define ANLPAR_NEXT         0x8000  // LP Next-Page Transmission Request


//
// Bits in the ANER register (06h)
//
#define ANER_LPANABLE       0x0001


//
// Bits in the GBTCR register (09h)
//
#define GBTCR_1000TH        0x0100  // 1000BASE-T HDX Capability
#define GBTCR_1000TF        0x0200  // 1000BASE-T FDX Capability
#define GBTCR_ABL_GIGA      (GBTCR_1000TF | GBTCR_1000TH)


//
// Bits in the MARVELL_PSCR register
//
#define MARVELL_PSCR_MDI0_MEGA  0x0010
#define MARVELL_PSCR_MDI1_MEGA  0x0020
#define MARVELL_PSCR_MDI0_GIGA  0x0020
#define MARVELL_PSCR_MDI1_GIGA  0x0040


//
// Bits in the CICADA_ACSR register
//
#define CICADA_ACSR_MODE_SEL    0x0004


//
// Bits in the VIA_NWAYFRC register
//
#define VIA_NWAYFRC_ABL         0x0004




// Company ID
#define CID_MARVELL             0x0141
#define CID_CICADA              0x000F
#define CID_VIA                 0x0101
#define CID_BROADCOM            0x0020

// Module ID
// Note: The GIGA module we supported are listed here.
//       If not listed, it will be recognized as MEGA module.
#define MID_MARVELL_88E1000     0x0C50
#define MID_MARVELL_88E1111     0x0CC0
#define MID_CICADA_CIS8201      0xC410
#define MID_CICADA_CIS8211      0xC4B0
#define MID_VIA_VT6108          0x8F90
#define MID_VIA_VT6103          0x8F25  // single phy, VT3072
#define MID_BROADCOM_BCM5421    0x60E0  


// Phy module type code
#define PHYTYPE_STANDARD        0x00
#define PHYTYPE_MARVELL_MEGA    0x10
#define PHYTYPE_MARVELL_GIGA    0x11
#define PHYTYPE_CICADA_GIGA     0x21
#define PHYTYPE_VIA_MEGA        0x30
#define PHYTYPE_BROADCOM_GIGA   0x41

/*---------------------  Export Types  ------------------------------*/

/*---------------------  Export Macros  -----------------------------*/

/*---------------------  Export Classes  ----------------------------*/

/*---------------------  Export Variables  --------------------------*/

/*---------------------  Export Functions  --------------------------*/
BOOL SWMII_bReadU16(UINT8 byPortId, UINT8 byAddr, PUINT16 pwData);
BOOL SWMII_bWriteU16(UINT8 byPortId, UINT8 byAddr, UINT16 wData);

BOOL SWMII_bRegBitsOn(UINT8 byPortId, UINT8 byAddr, UINT16 wBitPtn);
BOOL SWMII_bRegBitsOff(UINT8 byPortId, UINT8 byAddr, UINT16 wBitPtn);

BOOL SWMII_bIsRegBitsOn(UINT8 byPortId, UINT8 byAddr, UINT16 wBitPtn);
BOOL SWMII_bIsRegBitsOff(UINT8 byPortId, UINT8 byAddr, UINT16 wBitPtn);

void SWMII_vSetAutoPollOn(void);
void SWMII_vSetAutoPollOff(void);

UINT8 SWMII_byGetPhyType(UINT8 byPortId);




#endif /* __SWMII_H__ */