swpci.c

vt6528芯片交换机API函数和文档运行程序

/*
 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
 * All rights reserved.
 *
 * This software is copyrighted by and is the sole property of
 * VIA Networking Technologies, Inc. This software may only be used
 * in accordance with the corresponding license agreement. Any unauthorized
 * use, duplication, transmission, distribution, or disclosure of this
 * software is expressly forbidden.
 *
 * This software is provided by VIA Networking Technologies, Inc. "as is"
 * and any express or implied warranties, including, but not limited to, the
 * implied warranties of merchantability and fitness for a particular purpose
 * are disclaimed. In no event shall VIA Networking Technologies, Inc.
 * be liable for any direct, indirect, incidental, special, exemplary, or
 * consequential damages.
 *
 *
 * File:    swpci.c
 *
 * Purpose:
 *
 * Author:  Henry Lin
 *
 * Date:    Aug 10, 2005
 *
 * Functions:
 *
 * Revision History:
 *
 */


#if !defined(__DEVICE_H__)
#include "device.h"
#endif
#if !defined(__SWITCH_H__)
#include "switch.h"
#endif
#if !defined(__SWREG_H__)
#include "swreg.h"
#endif
#if !defined(__SWPKT_H__)
#include "swpkt.h"
#endif
#if !defined(__SWPCI_H__)
#include "swpci.h"
#endif

#ifdef __SWITCH_CPUIF_PCI



/*---------------------  Static Definitions  ------------------------*/
#define DEBUG_SWPCI         0

#if DEBUG_SWPCI
#if !defined(__UASSERT_H__)
#include "uassert.h"
#endif
#define DBG_PRN_SWPCI       DBG_PRN
#else
#define DBG_PRN_SWPCI(...)  FUNC_NULL()
#endif

/*---------------------  Static Types  ------------------------------*/

/*---------------------  Static Macros  -----------------------------*/

/*---------------------  Static Classes  ----------------------------*/

/*---------------------  Static Variables  --------------------------*/

/*---------------------  Static Functions  --------------------------*/

/*---------------------  Export Variables  --------------------------*/
SPacketPage g_RxPktPage[DEF_RX_PAGE_NUM + 1];
SPacketPage g_TxPktPage[DEF_TX_PAGE_NUM + 1];

UINT32  g_u32TdStrtPageAddr, g_u32TdStopPageAddr, g_u32TdPktBnry;
UINT32  g_u32RdStrtPageAddr, g_u32RdStopPageAddr, g_u32RdPktCurr;

/*---------------------  Import Variables  --------------------------*/




void SWPCI_vMstrInit(void)
{
    UINT8   u8RegVal = 0, u8HCICsr;
    UINT32  u32PageSize = DEF_RX_PAGE_SIZE, u32TxPageSize = DEF_TX_PAGE_SIZE;



    // Page size
    u8RegVal &= ~CFG0_TD_PGS_128B;  //tx 256 bytes
    u8RegVal &= ~CFG0_RD_PGS_128B;  //rx 256 bytes
    SWPCICSR_vWriteU8(PGS_SIZE_OFF, u8RegVal);

    // Transmit packet to switch setting
    // Configure start address, stop address for page

    // align address to 128/256Byte boundary(if page size is 128/256 bytes)
    if (((UINT32)(&g_TxPktPage[0]) & (u32TxPageSize-1)) != 0) {
        g_u32TdStrtPageAddr = ((UINT32)(&g_TxPktPage[0]) & (~u32TxPageSize + 1));
        g_u32TdStrtPageAddr += u32TxPageSize;
        g_u32TdStopPageAddr = g_u32TdStrtPageAddr + (DEF_TX_PAGE_SIZE * DEF_TX_PAGE_NUM);
    }
    else {
        g_u32TdStrtPageAddr = (UINT32)(&g_TxPktPage[0]);
        g_u32TdStopPageAddr = (UINT32)(&g_TxPktPage[DEF_TX_PAGE_NUM]);
    }

    // let it be non-cache memory
    g_u32TdStrtPageAddr += ASIC_DMA_MEM_BASE;
    g_u32TdStopPageAddr += ASIC_DMA_MEM_BASE;

    g_u32TdPktBnry = g_u32TdStrtPageAddr;

    SWPCICSR_vWriteU32(TD_STRT_PAGE_ADDR, g_u32TdStrtPageAddr );
    SWPCICSR_vWriteU32(TD_STOP_PAGE_ADDR, g_u32TdStopPageAddr );
    SWPCICSR_vWriteU32(TD_PKT_BNRY_ADDR, g_u32TdPktBnry );
   

    // Receive packet from switch setting
    // Configure start address, stop address for page
    
    // align address to 128/256Byte boundary(if page size is 128/256 bytes)
    if (((UINT32)(&g_RxPktPage[0]) & (u32PageSize-1)) != 0) {
        g_u32RdStrtPageAddr = ((UINT32)(&g_RxPktPage[0]) & (~u32PageSize + 1));
        g_u32RdStrtPageAddr += u32PageSize;
        g_u32RdStopPageAddr = g_u32RdStrtPageAddr + (DEF_RX_PAGE_SIZE * DEF_RX_PAGE_NUM);
    }
    else{
        g_u32RdStrtPageAddr = (UINT32)(&g_RxPktPage[0]);
        g_u32RdStopPageAddr = (UINT32)(&g_RxPktPage[DEF_RX_PAGE_NUM]);;
    }

    // let it be non-cache memory
    g_u32RdStrtPageAddr += ASIC_DMA_MEM_BASE;
    g_u32RdStopPageAddr += ASIC_DMA_MEM_BASE;

    g_u32RdPktCurr      = g_u32RdStrtPageAddr;

    SWPCICSR_vWriteU32(RD_STRT_PAGE_ADDR, g_u32RdStrtPageAddr );
    SWPCICSR_vWriteU32(RD_STOP_PAGE_ADDR, g_u32RdStopPageAddr );
    SWPCICSR_vWriteU32(RD_PKT_CURR_ADDR, g_u32RdPktCurr );

    // Write (or check) SW CSR 0x0008h bit 5 to master mode.
    PCIMEM_Read8((g_u32SwMemBA + CPUIF_HOSTIF_CFG), &u8RegVal);
    u8RegVal |= HOSTIF_MASTER_MODE;
    PCIMEM_Write8((g_u32SwMemBA + CPUIF_HOSTIF_CFG), u8RegVal);

    // Write (or check) HCI CSR 0x00h to enable BS2H_EN, BH2S_EN, PH2S_EN and .
    u8HCICsr = CR0_BS2H_EN | CR0_BH2S_EN | CR0_PH2S_EN | CR0_PS2H_EN;
    PCIIO_Write8((g_u32SwIoBA + CR0_OFF), u8HCICsr);
}



void SWPCI_vBusErrHandler(void)
{
    UINT8   u8RegVal;
    UINT16  u16IrqMask;


    //Dequeue hold cpu port
    SWREG_vWriteU8(QUECTL_DEQUE_HOLD + 3, DEQUE_HOLD_CPU);

    //Disable cpuio output port enable (OPORT_EN)
    SWREG_vReadU8(CPUPORT_CFG, &u8RegVal);
    u8RegVal &= ~CPU_CFG_RX_ENABLE;
    SWREG_vWriteU8(CPUPORT_CFG, u8RegVal);

    //Write 0x03(SFRST, FORSRST) to reset HCI DMA engine
    SWPCICSR_vWriteU8(CR0_OFF + 3, (CR3_FORSRST|CR3_SFRST_DONE) );
    
    //Wait HCI reset stable (by read SFRST=0)
    SWPCICSR_bWaitStatus(CR0_OFF + 3, CR3_SFRST_DONE, FALSE);

    //Enable HCI interrupt mask, ISR0/ISR1/ISR2 interrupts
    SWPCICSR_vWriteU32(IMR_OFF, (((UINT32)ISR3_ALL << 24) | ( ISR2_ALL << 16) | 
                              (ISR1_ALL << 8)  | ( ISR0_ALL )) );

    //Enable 0x00 PS2H_EN, and configure RD_RING and RD_PGS again
    SWPCI_vMstrInit();

    //Enable SW CSR 0x0004 irq mask
    SWREG_vReadU16(CPUIF_IRQ_MASK, &u16IrqMask);
    u16IrqMask |= (IRQ_STATUS_PKT_RX);
    SWREG_vWriteU16(CPUIF_IRQ_MASK, u16IrqMask);

    //Enable cpu output port (OPORT_EN) again
    SWREG_vReadU8(CPUPORT_CFG, &u8RegVal);
    u8RegVal |= CPU_CFG_RX_ENABLE;
    SWREG_vWriteU8(CPUPORT_CFG, u8RegVal);

    //Disable dequeue hold
    SWREG_vWriteU8(QUECTL_DEQUE_HOLD + 3, 0x00);
}


//
// if bWaitCond == TRUE, will wait the u8StsBitPtn be set,
// if bWaitCond == FALSE, will wait the u8StsBitPtn be cleared.
//
BOOL SWPCICSR_bWaitStatus (UINT16 u16Off, UINT8 u8StsBitPtn, BOOL bWaitCond)
{
    UINT8   u8Status;
    UINT16  ui;



    // Loop to wait for specified register bit pattern
    for (ui = 0; ui < MAX_LOOP_TIMEOUT; ui++) {
        SWPCICSR_vReadU8(u16Off, &u8Status);    // read register status
        // Check if wait condition matched
        if ((bWaitCond == TRUE) && ((u8Status & u8StsBitPtn) == u8StsBitPtn))
            return TRUE;
        else if ((bWaitCond == FALSE) && ((u8Status & u8StsBitPtn) == 0))
            return TRUE;
    }

    // timeout
    return FALSE;
}


#endif  //__SWITCH_CPUIF_PCI