📄 swsys.c
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} /* end SWSYS_bBufInit */
void SWSYS_vSwitchInit (void)
{
UINT8 u8Ver, u8RegVal;
// MIB Enable
SWREG_vBitsOnU8(INITCTL_MIB_EN, MIB_ENABLE);
// Set 0x415[7] = 0, if 1, many to one testing will loss packet
// Set 0x416[4] = 0, if 1, many to one testing will loss packet
SWREG_vBitsOffU8(INITCTL_BASIC_FUNC_CFG + 1, FUNC_CFG_DEADLOCK_RELIEF_EN);
SWREG_vBitsOffU8(INITCTL_BASIC_FUNC_CFG + 2, FUNC_CFG_FC_VIO_EN);
SWSYS_vGetChipVer(&u8Ver);
// Set CPU threshold
if (u8Ver >= 1) {
SWREG_vReadU8(RESMGMT_CPU_ENTER_CONG_THR, &u8RegVal);
SWREG_vWriteU8(RESMGMT_CPU_ENTER_CONG_THR, ((u8RegVal + 7) / 8));
SWREG_vReadU8((RESMGMT_CPU_ENTER_CONG_THR + 1), &u8RegVal);
SWREG_vWriteU8((RESMGMT_CPU_ENTER_CONG_THR + 1), ((u8RegVal + 7) / 8));
SWREG_vReadU8((RESMGMT_CPU_ENTER_CONG_THR + 2), &u8RegVal);
SWREG_vWriteU8((RESMGMT_CPU_ENTER_CONG_THR + 2), ((u8RegVal + 7) / 8));
SWREG_vReadU8((RESMGMT_CPU_ENTER_CONG_THR + 3), &u8RegVal);
SWREG_vWriteU8((RESMGMT_CPU_ENTER_CONG_THR + 3), ((u8RegVal + 7) / 8));
SWREG_vReadU8(RESMGMT_CPU_LEAVE_CONG_THR, &u8RegVal);
SWREG_vWriteU8(RESMGMT_CPU_LEAVE_CONG_THR, ((u8RegVal + 7) / 8));
}
// Apply CPU threshold set
SWREG_vWriteU8(RESMGMT_CPU_THR_ATTR, 0x01);
// Patch : set "PAD Delay"(reg. 0x041C-1D=0x55-55) for patch
// SMII mode receive FCS error on Y0 of PCB(VN0088A).
SWREG_vWriteU16(INITCTL_PAD_DELAY_CFG, 0x5555);
// Patch Qos
if (u8Ver == 1) {
SWREG_vWriteU8(RESMGMT_ENTER_CONG_THR1, 220);
SWREG_vWriteU8(RESMGMT_ENTER_CONG_THR1 + 1, 230);
SWREG_vWriteU8(RESMGMT_ENTER_CONG_THR1 + 2, 240);
SWREG_vWriteU8(RESMGMT_ENTER_CONG_THR1 + 3, 255);
SWREG_vWriteU8(RESMGMT_LEAVE_CONG_THR1, 200);
SWREG_vWriteU8(RESMGMT_ENTER_CONG_THR2, 220);
SWREG_vWriteU8(RESMGMT_ENTER_CONG_THR2 + 1, 230);
SWREG_vWriteU8(RESMGMT_ENTER_CONG_THR2 + 2, 240);
SWREG_vWriteU8(RESMGMT_ENTER_CONG_THR2 + 3, 255);
SWREG_vWriteU8(RESMGMT_LEAVE_CONG_THR2, 200);
SWREG_vWriteU8(RESMGMT_INGRS_BUF_USAGE_THR, 10);
SWREG_vWriteU8(RESMGMT_INGRS_BUF_USAGE_THR + 1, 8);
SWREG_vWriteU8(RESMGMT_INGRS_BUF_USAGE_THR + 2, 10);
SWREG_vWriteU8(RESMGMT_INGRS_BUF_USAGE_THR + 3, 8);
}
// Patch : none IP SNAP with tag packet will always be ARP packet
s_vPatchNonArpToCpu();
}
void SWSYS_vSwitchResetSignal(void)
{
// reset switch
PLAT_vSetMacResetPin(0);
// reset phy
PLAT_vSetPhyResetPin(0);
PLAT_vDelayLoop(1);
// de-assert reset signal
PLAT_vSetMacResetPin(1);
PLAT_vDelayLoop(1);
// de-assert reset signal
PLAT_vSetPhyResetPin(1);
// wait for phy initialize completed
PLAT_vDelayLoop(40);
}
BOOL SWSYS_bSwitchSramBIST (UINT8 byMemType)
{
BOOL bBistOK = TRUE;
UINT16 wStatus;
UINT32 dwStatus;
UINT8 byOldBistCfg;
SWREG_vReadU8(SRAMCTL_GBL_BIST_CFG, &byOldBistCfg);
if (byMemType == MEM_MOSYS) {
// Trigger BIST and wait for execution finished
SWREG_vWriteU8(SRAMCTL_GBL_BIST_CFG,
BIST_CFG_BIST_ENABLE | BIST_CFG_MOSYS_BIST_START);
if (!SWREG_bWaitStatus(SRAMCTL_MOSYS_BIST_STATUS+1,
(MOSYS_BIST_STATUS_OK >>8), TRUE)) {
bBistOK = FALSE;
goto exit;
}
// Return BIST result
SWREG_vReadU16(SRAMCTL_MOSYS_BIST_STATUS, &wStatus);
if ((wStatus & MOSYS_BIST_STATUS_ERR_MSK) != 0) {
bBistOK = FALSE;
goto exit;
}
}
else if (byMemType == MEM_CAM) {
// Trigger BIST and wait for execution finished
SWREG_vWriteU8(SRAMCTL_GBL_BIST_CFG,
BIST_CFG_BIST_ENABLE | BIST_CFG_CAM_BIST_START);
if (!SWREG_bWaitStatus(SRAMCTL_CAM_BIST_STATUS+2, (CAM_BIST_STATUS_OK>>16), TRUE)) {
bBistOK = FALSE;
goto exit;
}
// Return BIST result
SWREG_vReadU32(SRAMCTL_CAM_BIST_STATUS, &dwStatus);
if ((dwStatus & CAM_BIST_STATUS_ERR_MSK) != 0) {
bBistOK = FALSE;
goto exit;
}
}
else if (byMemType == MEM_ARTISAN) {
// Trigger BIST and wait for execution finished
SWREG_vWriteU8(SRAMCTL_GBL_BIST_CFG,
BIST_CFG_BIST_ENABLE | BIST_CFG_ARTISAN_BIST_START);
if (!SWREG_bWaitStatus(SRAMCTL_ATS_BIST_STATUS+2,
(ATS_BIST_STATUS_OK>>16), TRUE)) {
bBistOK = FALSE;
goto exit;
}
// Return BIST result
SWREG_vReadU16(SRAMCTL_NON_REPAIR_STATUS, &wStatus);
if ((wStatus & NON_REPAIR_STATUS_ATS_MSK) != 0) {
bBistOK = FALSE;
goto exit;
}
}
else {
return FALSE;
}
exit:
// Restore BIST enable after BIST Test
SWREG_vWriteU8(SRAMCTL_GBL_BIST_CFG, byOldBistCfg);
return bBistOK;
}
void SWSYS_vSetAutoPollOn (void)
{
SWREG_vWriteU8(PHYCTL_CMD, PHY_CMD_EN_AUTO);
SWREG_bWaitStatus(PHYCTL_STATUS, PHY_STATUS_AUTOPOLL, TRUE);
}
void SWSYS_vSetAutoPollOff (void)
{
SWREG_vWriteU8(PHYCTL_CMD, PHY_CMD_DIS_AUTO);
SWREG_bWaitStatus(PHYCTL_STATUS, PHY_STATUS_AUTOPOLL, FALSE);
}
void SWSYS_vBoardInit (void)
{
UINT uu;
UINT8 au8EthAddr[MAC_ADDR_SIZE];
// Trigger MAC & PHY reset signal
SWSYS_vSwitchResetSignal();
#ifdef __SWITCH_CPUIF_PCI
// scan switch device on PCI bus, then we can use it
PCILIB_Scan(&g_u32SwIoBA, &g_u32SwMemBA);
#endif
if (!SWSYS_bBufInit()) return;
// Set system initial hardware configuration
SWSYS_vSwitchInit();
// Enable phy autopolling
SWSYS_vSetAutoPollOn();
// It should be run when MAC resets and after hardware are all ready.
// get mac address from eeprom and set it switch
for (uu = 0; uu < MAC_ADDR_SIZE; uu++) {
NVRAM_bReadU8(NVR_ADDR_MAC_ADDR + uu, au8EthAddr + uu);
}
SWPKT_vSetMacAddress(au8EthAddr);
// Setup Interrupt Vector
#ifdef __SWITCH_CPUIF_PCI
ISR_vSetIntHandlers(INT_OFFSET_PCI_H, SWSYS_vIsrIntaAss);
#else // local bus
#ifdef __CPU_S3C2510A
ISR_vSetIntHandlers(VEC_EXT5_INT, ISR_vSwitch);
#else
ISR_vSetIntHandlers(VEC_EXT0_INT, ISR_vSwitch);
#endif
#endif
// ISR_vSwitchIntEnable();
}
void SWSYS_vBoardShutdown (void)
{
// release packet driver
SWPKT_vDrvClose();
// Unset Interrupt Vector
ISR_vSwitchIntDisable();
ISR_vSetIntHandlers(VEC_EXT0_INT, ISR_vDummyHandler);
// disabled all interrupt and cache
ISR_vIntDisable();
PLAT_vCacheDisable();
}
void SWSYS_vBoardReboot (void)
{
PLAT_vBoardReboot();
}
#if (SUPPORT_2M_PKT_MEM)
/************************************************************************
* This function allocates only 2Mbits packet buffer from the hw buffer pool
************************************************************************/
static BOOL s_bPktMemAlloc(void)
{
UINT8 u8Sts, u8Valid0, u8Valid1, au8Data[SRAM_ENTRY_SIZE_4Byte], byOldBistCfg;
UINT16 u16Len = 1024, u16All = 2048, u16Head[4], u16Tail[4];
UINT32 u32Addr;
u8Valid0 = u8Valid1 = 0;
//Using BIST to find the normal Packet Memory
SWREG_vReadU8(SRAMCTL_GBL_BIST_CFG, &byOldBistCfg);
SWREG_vWriteU8(SRAMCTL_GBL_BIST_CFG,
BIST_CFG_BIST_ENABLE | BIST_CFG_MOSYS_BIST_START);
if (!SWREG_bWaitStatus(SRAMCTL_MOSYS_BIST_STATUS+1,
(MOSYS_BIST_STATUS_OK >>8), TRUE)) {
return FALSE;
}
SWREG_vWriteU8(SRAMCTL_GBL_BIST_CFG, byOldBistCfg);
//-----assign valid Mosys SRAM
SWREG_vReadU8(SRAMCTL_NON_REPAIR_STATUS, &u8Sts);
if((u8Sts & NON_REPAIR_STATUS_PM0) == 0){
//PM0 is good
u8Valid0 = 0;
if((u8Sts & NON_REPAIR_STATUS_PM1) == 0)
u8Valid1 = 1;
else if((u8Sts & NON_REPAIR_STATUS_PM2) == 0)
u8Valid1 = 2;
else if((u8Sts & NON_REPAIR_STATUS_PM3) == 0)
u8Valid1 = 3;
}
else{
if((u8Sts & NON_REPAIR_STATUS_PM1) == 0){
//PM1 is good
u8Valid0 = 1;
if(u8Sts & NON_REPAIR_STATUS_PM2)
u8Valid1 = 2;
else if((u8Sts & NON_REPAIR_STATUS_PM3) == 0)
u8Valid1 = 3;
}
else{
if((u8Sts & NON_REPAIR_STATUS_PM2) == 0){
//PM2 is good
u8Valid0 = 2;
if(u8Sts & NON_REPAIR_STATUS_PM3)
u8Valid1 = 3;
}
}
}
//-----re-assign the head and tail of all Link Lists
u16Head[0] = u8Valid0 * u16Len;
u16Tail[0] = u16Head[0] + (u16All / 4) - 1;
u16Head[1] = u16Tail[0] + 1;
u16Tail[1] = u16Head[1] + (u16All / 4) - 1;
u16Head[2] = u8Valid1 * u16Len;
u16Tail[2] = u16Head[2] + (u16All / 4) - 1;
u16Head[3] = u16Tail[2] + 1;
u16Tail[3] = u16Head[3] + (u16All / 4) - 1;
//-----Enable buffer intialization
SWREG_vBitsOnU8(BUFCTL_INIT, BUF_INIT_HW_OK);
//-----write tail and head at same pointer to stop function of buffer controller
SWREG_vBitsOffU8(BUFCTL_BUF_CFG, BUF_CNTRL_LL0_3_EN); //Disable linked list 0~4
SWREG_vWriteU16(BUFCTL_FREE_LNK_LST0_TAIL, 0x0000);
SWREG_vWriteU16(BUFCTL_FREE_LNK_LST1_TAIL, 0x0400);
SWREG_vWriteU16(BUFCTL_FREE_LNK_LST2_TAIL, 0x0800);
SWREG_vWriteU16(BUFCTL_FREE_LNK_LST3_TAIL, 0x0C00);
SWREG_vBitsOnU8(BUFCTL_BUF_CFG, BUF_CNTRL_LL0_3_EN); //Enable linked list 0~4
SWREG_bWaitStatus(BUFCTL_INIT, BUF_INIT_HW_OK, TRUE);
//------ re-chain free link list:write segmement link of SRAM.
u32Addr = u16Tail[1];
u32Addr = (u32Addr << 2) + SRAM_SGMNT_LNK_BASE_ADDR;
STR_pvMemset(au8Data, 0, SRAM_ENTRY_SIZE_4Byte);
au8Data[0] = (UINT8)(u16Head[2] & 0xFF);
au8Data[1] = (UINT8)(u16Head[2] >> 8);
SWSRAM_bWriteEntry(u32Addr, au8Data);
//-----set Link List length = 512
SWREG_vWriteU16(BUFCTL_FREE_LNK_LST_LEN0, 512);
SWREG_vWriteU16(BUFCTL_FREE_LNK_LST_LEN1, 512);
SWREG_vWriteU16(BUFCTL_FREE_LNK_LST_LEN2, 512);
SWREG_vWriteU16(BUFCTL_FREE_LNK_LST_LEN3, 512);
//-----set head and tail
SWREG_vWriteU16(BUFCTL_FREE_LNK_LST0_HEAD, u16Head[0]);
SWREG_vWriteU16(BUFCTL_FREE_LNK_LST1_HEAD, u16Head[1]);
SWREG_vWriteU16(BUFCTL_FREE_LNK_LST2_HEAD, u16Head[2]);
SWREG_vWriteU16(BUFCTL_FREE_LNK_LST3_HEAD, u16Head[3]);
SWREG_vWriteU16(BUFCTL_FREE_LNK_LST0_TAIL, u16Tail[0]);
SWREG_vWriteU16(BUFCTL_FREE_LNK_LST1_TAIL, u16Tail[1]);
SWREG_vWriteU16(BUFCTL_FREE_LNK_LST2_TAIL, u16Tail[2]);
SWREG_vWriteU16(BUFCTL_FREE_LNK_LST3_TAIL, u16Tail[3]);
//-----Modify Threshold of Congestion Control
SWREG_vWriteU16(RESMGMT_LEAVE_SYS_XOFF_THR, 3500);
SWREG_vWriteU16(RESMGMT_ENTER_SYS_XOFF_THR, 3052);
SWREG_vWriteU16(RESMGMT_LEAVE_ALL_XOFF_THR, 2661);
SWREG_vWriteU16(RESMGMT_ENTER_ALL_XOFF_THR, 2312);
return TRUE;
}
#endif /* SUPPORT_2M_PKT_MEM */
static void s_vPatchNonArpToCpu(void)
{
UINT8 u8RegVal;
STcamEntry STcamEntryBuf;
SL2pACEntry SL2ACEntryBuf;
UINT8 u8EntryIndex = 246;
UINT16 u16ByteMsk = 0, u16MskType = 0;
UINT8 byTmpType[2];
// L2+ mirror to CPU port
SWREG_vReadU8(FWDCTL_MIRROR_PORT_CFG, &u8RegVal);
u8RegVal |= 0x1A;
SWREG_vWriteU8(FWDCTL_MIRROR_PORT_CFG, u8RegVal);
//*** ACL 0 ***//
//Set entry into TCAM table
STR_pvMemset(&STcamEntryBuf, 0 , sizeof(STcamEntry));
// DMAC_TYPE == broadcast
STcamEntryBuf.u8DmacType = 2;
u16MskType |= MSK_DMAC_TYPE;
//no matter Ipv4 or Non_ipv4 group,check this bit
u16MskType |= MSK_IPV4;
byTmpType[0] = 0x08;
byTmpType[1] = 0x06;
STcamEntryBuf.UCfg13B.au8AftSV[0] = byTmpType[0];
STcamEntryBuf.UCfg13B.au8AftSV[1] = byTmpType[1];
u16ByteMsk |= 0x0003; //unmaked 1st,2nd octet after SMAC or VLAN-tag (0000 0000 0000 0011 b)
#if defined(__LITTLE_ENDIAN)
// convert byte array
SWSRAM_vEndianConvert(&STcamEntryBuf.UCfg13B.au8AftSV[1],4);
SWSRAM_vEndianConvert(&STcamEntryBuf.UCfg13B.au8AftSV[5],4);
SWSRAM_vEndianConvert(&STcamEntryBuf.UCfg13B.au8AftSV[9],4);
#endif
// Insert entry into HW TCAM table
SWTCAM_bInsEntry(u8EntryIndex, &STcamEntryBuf,FALSE);
// Set entry into HW TCAM MASK table
STR_pvMemset(&STcamEntryBuf, 0 , sizeof(STcamEntry));
//UNMASK rules
SWTCAM_vUnMskEntry(&STcamEntryBuf, FALSE, u16MskType, u16ByteMsk);
#if defined(__LITTLE_ENDIAN)
// convert byte array
SWSRAM_vEndianConvert(&STcamEntryBuf.UCfg13B.au8AftSV[1],4);
SWSRAM_vEndianConvert(&STcamEntryBuf.UCfg13B.au8AftSV[5],4);
SWSRAM_vEndianConvert(&STcamEntryBuf.UCfg13B.au8AftSV[9],4);
#endif
// Insert entry into HW TCAM MASK table
SWTCAM_bInsEntry(u8EntryIndex, &STcamEntryBuf,TRUE);
// Set entry into ACTION CODE table
STR_pvMemset(&SL2ACEntryBuf, 0 , sizeof(SL2pACEntry));
SL2ACEntryBuf.bMirror = TRUE;
// Insert entry into HW ACTION CODE table
SWL2PAC_bInsEntry(u8EntryIndex, &SL2ACEntryBuf);
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