swsys.c

vt6528芯片交换机API函数和文档运行程序

/*
 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
 * All rights reserved.
 *
 * This software is copyrighted by and is the sole property of
 * VIA Networking Technologies, Inc. This software may only be used
 * in accordance with the corresponding license agreement. Any unauthorized
 * use, duplication, transmission, distribution, or disclosure of this
 * software is expressly forbidden.
 *
 * This software is provided by VIA Networking Technologies, Inc. "as is"
 * and any express or implied warranties, including, but not limited to, the
 * implied warranties of merchantability and fitness for a particular purpose
 * are disclaimed. In no event shall VIA Networking Technologies, Inc.
 * be liable for any direct, indirect, incidental, special, exemplary, or
 * consequential damages.
 *
 *
 * File:    swsys.c
 *
 * Purpose: Hardware accessing functions related to whole system
 *
 * Author:  Tevin Chen
 *
 * Date:    Jan 08, 2002
 *
 * Functions:
 *
 * Revision History:
 *
 */


#if !defined(__STR_H__)
#include "str.h"
#endif
#if !defined(__NVRAM_H__)
#include "nvram.h"
#endif
#if !defined(__PLATFORM_H__)
#include "platform.h"
#endif
#if !defined(__SWCFG_H__)
#include "swcfg.h"
#endif
#if !defined(__SWITCH_H__)
#include "switch.h"
#endif
#if !defined(__SWSRAM_H__)
#include "swsram.h"
#endif
#if !defined(__SWREG_H__)
#include "swreg.h"
#endif
#if !defined(__SWPKT_H__)
#include "swpkt.h"
#endif
#if !defined(__SWSYS_H__)
#include "swsys.h"
#endif
#if !defined(__SWL2PTB_H__)
#include "swl2ptb.h"
#endif




/*---------------------  Static Definitions  ------------------------*/
#define DEBUG_SYS           0
#define SUPPORT_2M_PKT_MEM  1           /* 1 = Support 2M bits pkt mem  */

#if DEBUG_SYS
#if !defined(__UASSERT_H__)
#include "uassert.h"
#endif
#define DBG_PRN_SYS         DBG_PRN
#else
#define DBG_PRN_SYS(...)    FUNC_NULL()
#endif

#define MAC_ADDR_SIZE       6           // 6 bytes

/*---------------------  Static Types  ------------------------------*/

/*---------------------  Static Macros  -----------------------------*/

/*---------------------  Static Classes  ----------------------------*/

/*---------------------  Static Variables  --------------------------*/
#if (SUPPORT_2M_PKT_MEM)
static BOOL s_bPktMemAlloc(void);
#endif
static void s_vPatchNonArpToCpu(void);

/*---------------------  Static Functions  --------------------------*/
#ifdef __SWITCH_CPUIF_PCI
void SWSYS_vIsr0HCI (void);
void SWSYS_vIsr1HCI (void);
void SWSYS_vIsr2HCI (void);
#endif

/*---------------------  Export Variables  --------------------------*/
PFN_HOOK g_pfnLinkChangeFunc = ISR_vDummyHandler;
struct SIsrCpuCntr g_SIsrCpuCntr; //TOCHECK

#ifdef __SWITCH_CPUIF_PCI
UINT32 g_u32SwIoBA = 0;
UINT32 g_u32SwMemBA = 0;
#endif




#ifdef __SWITCH_CPUIF_PCI

void PCI_CSR_INTR_View(void)
{
    UINT32   u32HCICsr;


    //Read the interrupt status HCI CSR 0x23h and 0x20h, and clear the interrupt (BRD2I)
    PCIIO_Read32((g_u32SwIoBA + ISR0_OFF), &u32HCICsr);
    DBG_PRN_SYS("\nISR0=0x%x ", (UINT8)u32HCICsr);
    DBG_PRN_SYS("\nISR1=0x%x ", (UINT8)(u32HCICsr>>8));
    DBG_PRN_SYS("\nISR2=0x%x ", (UINT8)(u32HCICsr>>16));
    DBG_PRN_SYS("\nISR3=0x%x \n", (UINT8)(u32HCICsr>>24));
}


//
// Interrupt Service Routines: When INTA# is asserted
//
void SWSYS_vIsrIntaAss (void)
{
    UINT8   u8StatusBits, u8IrqMask;
    UINT16  u16StatusBits, u16IrqMask;
    UINT32  uPciIntSt;



    uPciIntSt = ASIC_PCI_PCIINTST;

    // read mask
    PCIIO_Read8((g_u32SwIoBA + IMR_OFF + 3), &u8IrqMask);
    // read irq3 status(combination of ISR0,1,2 and SWI)
    PCIIO_Read8((g_u32SwIoBA + ISR0_OFF + 3), &u8StatusBits);
    u8StatusBits &= u8IrqMask;
    PCI_CSR_INTR_View();
    if ((u8StatusBits & ISR3_SWI) != 0) {
        SWREG_vReadU16(CPUIF_IRQ_STATUS, &u16StatusBits);
        SWREG_vReadU16(CPUIF_IRQ_MASK, &u16IrqMask);
        DBG_PRN_SYS("\n CPUIF_IRQ_STATUS=0x%x ", u16StatusBits);
        DBG_PRN_SYS("\n CPUIF_IRQ_MASK=0x%x ", u16IrqMask);
        ISR_vSwitch();
    }

    if ((u8StatusBits & ISR3_ISR0_STATUS) != 0) {
        SWSYS_vIsr0HCI();
    }
    if ((u8StatusBits & ISR3_ISR1_STATUS) != 0) {
        SWSYS_vIsr1HCI();
    }
    if ((u8StatusBits & ISR3_ISR2_STATUS) != 0) {
        SWSYS_vIsr2HCI();
    }

    ASIC_PCI_PCIINTST = uPciIntSt;
}


//
// Interrupt Service Routines: HCI ISR0
//
void SWSYS_vIsr0HCI (void)
{
    UINT8   u8StatusBits, u8IrqMask;


    // read imr
    PCIIO_Read8((g_u32SwIoBA + IMR_OFF), &u8IrqMask);
    // read irq status
    PCIIO_Read8((g_u32SwIoBA + ISR0_OFF), &u8StatusBits);
    u8StatusBits &= u8IrqMask;

    if ((u8StatusBits & ISR0_PTX0I) != 0) {
        PCIIO_Write8( (g_u32SwIoBA + ISR0_OFF), ISR0_PTX0I);
    }
    if ((u8StatusBits & ISR0_PTX1I) != 0) {
    }
    if ((u8StatusBits & ISR0_PTX2I) != 0) {
        PCIIO_Write8( (g_u32SwIoBA + ISR0_OFF), ISR0_PTX2I);
        DBG_PRN_SYS(" SYS: tx dma done.");
        g_SIsrCpuCntr.dwIsrWrPktDmaDone++;
        ISR_vWrPktDmaCompleted();

    }
    if ((u8StatusBits & ISR0_PRX0I) != 0) {
    }
    if ((u8StatusBits & ISR0_PRX1I) != 0) {
    }
    if ((u8StatusBits & ISR0_PRX2I) != 0) {
        DBG_PRN_SYS(" SYS: rx dma done.");
        g_SIsrCpuCntr.dwIsrRdPktDmaDone++;
        SWREG_vWriteU16(CPUIF_IRQ_STATUS, IRQ_STATUS_RDPKT_DMA_DONE);
        ISR_vRdPktDmaCompleted();
        PCIIO_Write8( (g_u32SwIoBA + ISR0_OFF), ISR0_PRX2I);
    }

}


//
// Interrupt Service Routines: HCI ISR1
//
void SWSYS_vIsr1HCI (void)
{
    UINT8   u8StatusBits, u8IrqMask;


    // read imr
    PCIIO_Read8((g_u32SwIoBA + IMR_OFF + 1), &u8IrqMask);
    // read irq status
    PCIIO_Read8((g_u32SwIoBA + ISR1_OFF), &u8StatusBits);
    u8StatusBits &= u8IrqMask;

    if ((u8StatusBits & ISR1_BWR0I) != 0) {
        g_SIsrCpuCntr.dwIsrMstrMemPostWrDone++;
        PCIIO_Write8( (g_u32SwIoBA + ISR1_OFF), ISR1_BWR0I);
        DBG_PRN_SYS("ISR1[8] :BH2S DMA post write switch done.\n");
    }
    if ((u8StatusBits & ISR1_BWR1I) != 0) {
    }
    if ((u8StatusBits & ISR1_BWR2I) != 0) {
        g_SIsrCpuCntr.dwIsrMstrMemWrDone++;
        PCIIO_Write8( (g_u32SwIoBA + ISR1_OFF), ISR1_BWR2I);
        DBG_PRN_SYS("ISR1[10] :BH2S DMA complete, block write  data are fetched in DMAC.\n");
    }
    if ((u8StatusBits & ISR1_BRD0I) != 0) {
    }
    if ((u8StatusBits & ISR1_BRD1I) != 0) {
    }
    if ((u8StatusBits & ISR1_BRD2I) != 0) {
        g_SIsrCpuCntr.dwIsrMstrMemRdDone++;
        PCIIO_Write8( (g_u32SwIoBA + ISR1_OFF), ISR1_BRD2I);
        DBG_PRN_SYS("ISR1[14] :BS2H embedded memory block read  DMA prefetch Complete.\n");
    }

}


//
// Interrupt Service Routines: HCI ISR2
//
void SWSYS_vIsr2HCI (void)
{
    UINT8   u8StatusBits, u8IrqMask;


    // read imr
    PCIIO_Read8((g_u32SwIoBA + IMR_OFF + 2), &u8IrqMask);
    // read irq status
    PCIIO_Read8((g_u32SwIoBA + ISR2_OFF), &u8StatusBits);
    u8StatusBits &= u8IrqMask;

    if ((u8StatusBits & ISR2_BSE0I) != 0) {
        PCIIO_Write8( (g_u32SwIoBA + ISR2_OFF), ISR2_BSE0I);
        DBG_PRN_SYS("ISR2[16] :ISR2_BSE0I.\n");
    }
    if ((u8StatusBits & ISR2_BSE1I) != 0) {
        PCIIO_Write8( (g_u32SwIoBA + ISR2_OFF), ISR2_BSE1I);
        DBG_PRN_SYS("ISR2[17] :ISR2_BSE1I.\n");
    }
    if ((u8StatusBits & ISR2_BSE2I) != 0) {
        PCIIO_Write8( (g_u32SwIoBA + ISR2_OFF), ISR2_BSE2I);
        DBG_PRN_SYS("ISR2[18] :ISR2_BSE2I.\n");
    }
    if ((u8StatusBits & ISR2_BSE3I) != 0) {
        PCIIO_Write8( (g_u32SwIoBA + ISR2_OFF), ISR2_BSE3I);
        DBG_PRN_SYS("ISR2[19] :ISR2_BSE3I.\n");
    }
    if ((u8StatusBits & ISR2_UDPI) != 0) {
        DBG_PRN_SYS("ISR2[23] :ISR2_UDPI.\n");
    }

}

#endif




//
// Interrupt Service Routines: SWITCH
//
void ISR_vSwitch (void)
{
    UINT16  u16StatusBits;
    UINT16  u16IrqMask;

    // first, disable switch interrupt
    ISR_vSwitchIntDisable();

    // read irq status
    SWREG_vReadU16(CPUIF_IRQ_STATUS, &u16StatusBits);
    DBG_PRN_SYS(" SYS: CPUIF_ISR = 0x%04X", u16StatusBits);
    // don't process those bits that is mask out
    SWREG_vReadU16(CPUIF_IRQ_MASK, &u16IrqMask);
    u16StatusBits &= u16IrqMask;

    if ((u16StatusBits & IRQ_STATUS_PKT_RX) != 0) {
        DBG_PRN_SYS(" SYS: rx interrupt in.");
        g_SIsrCpuCntr.dwIsrPktRx++;
        ISR_vRecvPkt();
    }

    if ((u16StatusBits & IRQ_STATUS_PKT_TX) != 0) {
        DBG_PRN_SYS(" SYS: tx interrupt in.");
        g_SIsrCpuCntr.dwIsrPktTxFinish++;
        ISR_vSendPkt();
    }

    if ((u16StatusBits & IRQ_STATUS_LINK_CHG) != 0) {
        DBG_PRN_SYS(" SYS: link-change interrupt in.");
        g_SIsrCpuCntr.dwIsrLnkChg++;
        SWREG_vWriteU16(CPUIF_IRQ_STATUS, IRQ_STATUS_LINK_CHG);
        g_pfnLinkChangeFunc();
    }

    if ((u16StatusBits & IRQ_STATUS_RDPKT_DMA_DONE) != 0) {
        g_SIsrCpuCntr.dwIsrRdPktDmaDone++;
        SWREG_vWriteU16(CPUIF_IRQ_STATUS, IRQ_STATUS_RDPKT_DMA_DONE);
        ISR_vRdPktDmaCompleted();
    }

    if ((u16StatusBits & IRQ_STATUS_WRPKT_DMA_DONE) != 0) {
        g_SIsrCpuCntr.dwIsrWrPktDmaDone++;
        SWREG_vWriteU16(CPUIF_IRQ_STATUS, IRQ_STATUS_WRPKT_DMA_DONE);
        ISR_vWrPktDmaCompleted();
    }

    // only uses by analyzer
    if ((u16StatusBits & IRQ_STATUS_INIT_OK) != 0) {
        g_SIsrCpuCntr.dwChipInitOk++;
        SWREG_vWriteU16(CPUIF_IRQ_STATUS, IRQ_STATUS_INIT_OK);
    }
    if ((u16StatusBits & IRQ_STATUS_LOG_OVER_THR) != 0) {
        g_SIsrCpuCntr.dwIsrLogTblOverThr++;
        SWREG_vWriteU16(CPUIF_IRQ_STATUS, IRQ_STATUS_LOG_OVER_THR);
    }
    if ((u16StatusBits & IRQ_STATUS_MEM_DMA_DONE) != 0) {
        g_SIsrCpuCntr.dwIsrMemDmaDone++;
        SWREG_vWriteU16(CPUIF_IRQ_STATUS, IRQ_STATUS_MEM_DMA_DONE);
    }
    if ((u16StatusBits & IRQ_STATUS_LOG_FULL) != 0) {
        g_SIsrCpuCntr.dwIsrLogTblFull++;
        SWREG_vWriteU16(CPUIF_IRQ_STATUS, IRQ_STATUS_LOG_FULL);
    }
    if ((u16StatusBits & IRQ_STATUS_BUF_STARVATION) != 0) {
        g_SIsrCpuCntr.dwIsrBufStarve++;
        SWREG_vWriteU16(CPUIF_IRQ_STATUS, IRQ_STATUS_BUF_STARVATION);
    }
    if ((u16StatusBits & IRQ_STATUS_BSF) != 0) {
        g_SIsrCpuCntr.dwIsrBSF++;
        SWREG_vWriteU16(CPUIF_IRQ_STATUS, IRQ_STATUS_BSF);
    }

    // finally, enable switch interrupt
    ISR_vSwitchIntEnable();
}

/************************************************************************
 * Switch Buffer Init
 ************************************************************************/
BOOL SWSYS_bBufInit(void)
{
    BOOL        bRet;
    
#if (SUPPORT_2M_PKT_MEM)
    /*
     * Read from Switch Binding Option (reg 0x410)
     *  if Reg_0x410[3] == 1, means switch support 4 Mb packet mem,
     *  else switch support only 2 Mb packet mem
     */
    if (SWREG_bIsBitsOnU8(0x410, 0x08))
    {
        // RAM BIST
        bRet = SWSYS_bSwitchSramBIST(MEM_MOSYS);
        bRet &= SWSYS_bSwitchSramBIST(MEM_CAM);
        bRet &= SWSYS_bSwitchSramBIST(MEM_ARTISAN);
        if (!bRet)  goto exit;
        
        // Use BUF_INIT_HW_OK to initialize buffer,
        // if using BUF_INIT_SW_OK, we need to handling the buffer linking by S/W
        SWREG_vBitsOnU8(BUFCTL_INIT, BUF_INIT_HW_OK);
        bRet = SWREG_bWaitStatus(BUFCTL_INIT, BUF_INIT_HW_OK, TRUE);
    }
    else
    {
        bRet = s_bPktMemAlloc();
    }
#else
    // RAM BIST
    bRet = SWSYS_bSwitchSramBIST(MEM_MOSYS);
    bRet &= SWSYS_bSwitchSramBIST(MEM_CAM);
    bRet &= SWSYS_bSwitchSramBIST(MEM_ARTISAN);
    if (!bRet)  goto exit;
    
    // Use BUF_INIT_HW_OK to initialize buffer,
    // if using BUF_INIT_SW_OK, we need to handling the buffer linking by S/W
    SWREG_vBitsOnU8(BUFCTL_INIT, BUF_INIT_HW_OK);
    bRet = SWREG_bWaitStatus(BUFCTL_INIT, BUF_INIT_HW_OK, TRUE);
#endif
exit:
    return(bRet);