switch.h

vt6528芯片交换机API函数和文档运行程序

//--------------------------------------
// 0600H Buffer Control
//--------------------------------------
//
// Bits in the BUFCTL_BUF_CFG register
//
#define BUF_CNTRL_LL0_3_EN              0x0F


//
// Bits in the BUFCTL_INIT register
//
#define BUF_INIT_HW_OK                  0x01
#define BUF_INIT_SW_OK                  0x02


//--------------------------------------
// 0700H Resource Management
//--------------------------------------

//
// Bits in the RESMGMT_MANAGER_CFG register
//
#define BSF_BCAST_ENABLE                0x01
#define BSF_IP_MCAST_ENABLE             0x02
#define BSF_CTRL_PKT_ENABLE             0x04
#define BSF_FLD_ENABLE                  0x08
#define BSF_RATE_1DIV2                  0x00
#define BSF_RATE_1DIV4                  0x10
#define BSF_RATE_1DIV8                  0x20
#define BSF_RATE_1DIV16                 0x30
#define BSF_RATE_MSK                    0x30


//
// Bits in the RESMGMT_PORT24_25_CFG register
//
#define IRC_PORT24_USE_SET2             0x10
#define IRC_PORT25_USE_SET2             0x20


//
// Bits in the RESMGMT_THR1_ATTR register
//
#define RESMGMT_THR_APPLY               0x01


//
// Bits in the RESMGMT_SYS_XOFF_WIN register
//
#define RESMGMT_WIN_XON                 0x00
#define RESMGMT_WIN_XOFF                0x01
#define RESMGMT_WIN_ALL_XOFF            0x03


//--------------------------------------
// 0800H SRAM BIST Control
//--------------------------------------

//
// Bits in the SRAMCTL_GBL_BIST_CFG register
//
#define BIST_CFG_ARTISAN_BIST_START     0x01
#define BIST_CFG_CAM_BIST_START         0x02
#define BIST_CFG_MOSYS_BIST_START       0x04
#define BIST_CFG_MEM_INIT_START         0x08
#define BIST_CFG_BIST_ENABLE            0x10
#define BIST_CFG_CAM_INIT_START         0x20


//
// Bits in the SRAMCTL_NON_REPAIR_STATUS register
//
#define NON_REPAIR_STATUS_MSK           0x3FFF
#define NON_REPAIR_STATUS_ATS_MSK       0x7800
#define NON_REPAIR_STATUS_PM0           0x01
#define NON_REPAIR_STATUS_PM1           0x02
#define NON_REPAIR_STATUS_PM2           0x04
#define NON_REPAIR_STATUS_PM3           0x08


//
// Bits in the SRAMCTL_MOSYS_BIST_STATUS register
//
#define MOSYS_BIST_STATUS_ERR_MSK       0x0FFF
#define MOSYS_BIST_STATUS_BUSY          0x1000
#define MOSYS_BIST_STATUS_OK            0x2000


//
// Bits in the SRAMCTL_CAM_BIST_STATUS register
//
#define CAM_BIST_STATUS_ERR_MSK         0x037777
#define CAM_BIST_STATUS_BUSY            0x040000
#define CAM_BIST_STATUS_OK              0x080000


//
// Bits in the SRAMCTL_ATS_BIST_STATUS register
//
#define ATS_BIST_STATUS_ERR_MSK         0x01FFFF
#define ATS_BIST_STATUS_BUSY            0x020000
#define ATS_BIST_STATUS_OK              0x040000


//--------------------------------------
// 0C00H Advanced Forwarding Table Control
//--------------------------------------

//
// Bits in the ADVFWD_SCOPE0_OPT register
//
#define SCOPE_OPT_LOOKUP_MISS_DISCARD   0x01
#define SCOPE_OPT_VIOLATOR_DETECT_EN    0x02
#define SCOPE_OPT_VIOLATOR_PROCS_EN     0x04


//--------------------------------------
// 1000H-1640H Port 0-25 Configuration
//--------------------------------------


//
// Bits in the PORTCFG_TRUNK_CRITERIA_BASE register
//
#define TRUNK_CFG_ENABLE                0x1000



//
// Bits in the PORTCFG_VLAN_CFG_BASE register
//
#define VLAN_CFG_PVID_MSK               0x0FFF
#define VLAN_CFG_INTERNAL_VLAN          0x1000
#define VLAN_CFG_INT_PVID_MSK           0x1FFF
#define VLAN_CFG_CLASS_METHOD0          0x0000
#define VLAN_CFG_CLASS_METHOD1          0x2000
#define VLAN_CFG_CLASS_METHOD2          0x4000
#define VLAN_CFG_CLASS_METHOD3          0x6000
#define VLAN_CFG_CLASS_METHOD4          0x8000
#define VLAN_CFG_CLASS_MSK              0xE000

//
// Bits in the PORTCFG_VLAN_MODE_BASE register
//
#define VLAN_CFG_VERBATIM_MODE          0x20



//
// Bits in the PORTCFG_PRIO_CFG_BASE register
//
// For forward compatible purpose
#define PRIO_PORT_DIS                   0x00
#define PRIO_PORT_LOW                   0x08    // low map to priority0
#define PRIO_PORT_HIGH                  0x0F    // high map to priority7

#define PRIO_PORT_MSK                   0x0F
#define PRIO_PORT_SEL                   0x08
#define PRIO_VLAN_TAG_SEL               0x10
#define PRIO_VLAN_SEL                   0x20
#define PRIO_TOS_DSCP_SEL               0x40
#define PRIO_L2P_ACT_SEL                0x80


//
// Bits in the PORTCFG_PRIO_ADJ_BASE register
//
#define PRIO_PROPAGATE_EN               0x01
#define PRIO_ADJ_EN                     0x02


//
// Bits in the PORTCFG_INGRS_FLTR_BASE register
//
#define INGRS_FLTR_DISABLE              0x00
#define INGRS_FLTR_NOTMBR               0x01    // drop not member packet, and so on.
#define INGRS_FLTR_UNTAG                0x02
#define INGRS_FLTR_NOTMBR_UNTAG         0x03
#define INGRS_FLTR_TAGGED               0x04
#define INGRS_FLTR_NOTMBR_TO_CPU        0x08
#define INGRS_FLTR_BPDU                 0x10
#define INGRS_FLTR_LACP                 0x20
#define INGRS_FLTR_8021X                0x40


//
// Bits in the PORTCFG_BSF_CFG_BASE register
//
#define BSF_ENABLE                  0x01


//
// Bits in the PORTCFG_INGRS_RATE_CFG_BASE register
//
#define INGRS_RATE_CTRL_ENABLE          0x0400
#define INGRS_RATE_TIME_1000us          0x0000
#define INGRS_RATE_TIME_100us           0x0100
#define INGRS_RATE_TIME_10us            0x0200


//
// Bits in the PORTCFG_EGRS_RATE_CFG_BASE register
//
#define EGRS_RATE_CTRL_ENABLE           0x8000
#define EGRS_RATE_CNST_M_MSK            0x07FF
#define EGRS_RATE_CNST_R_MSK            0x7800




//--------------------------------------
// Definition for HCI CRS Registers
//--------------------------------------
#define CR0_OFF             0x00    //Command Register CR0
#define DCR0_OFF            0x08    //DMA Control Register0
#define PDP_OFF             0x10    //Packet read/write data port
#define RDP_OFF             0x14    //Register read/write data
#define RAP_OFF             0x18    //Internal register address
#define ISR0_OFF            0x20    //
#define ISR1_OFF            0x21    //
#define ISR2_OFF            0x22    //
#define ISR3_OFF            0x23    //
#define IMR_OFF             0x24    //Interrupt mask
#define POR_OFF             0x2E    //POR_Status
#define PGS_SIZE_OFF        0x3E    //CFG0  Description

#define RD_STRT_PAGE_ADDR   0x40    //RD_STRT_PAGE_ADDR
#define RD_STOP_PAGE_ADDR   0x44    //RD_STOP_PAGE_ADDR
#define RD_PKT_CURR_ADDR    0x48    //RD_PKT_CURR_ADDR
#define RD_PKT_BC           0x4C    //Current received packet byteCounts.

#define TD_STRT_PAGE_ADDR   0x50    //TD_STRT_PAGE_ADDR
#define TD_STOP_PAGE_ADDR   0x54    //TD_STOP_PAGE_ADDR
#define TD_PKT_BNRY_ADDR    0x58    //The starting address of every Tx Packet DMA
#define TD_PKT_BC           0x5C    //CPU initiated Tx packet request byte count.

#define BLK_READ_DMA_BASE_ADDR_OFF  0x60    //BLK_READ_DMA_START_ADDR
#define BLK_READ_BC         0x68    //CPU memory block read request byte count.
#define BLK_WRITE_DMA_BASE_ADDR_OFF 0x70    //BLK_WRITE_DMA_START_ADDR.
#define BLK_WRITE_BC        0x78    //CPU memory block write request byte count.


//
// Bits in the CR0 register
//
#define CR0_PS2H_EN                     0x01
#define CR0_PH2S_EN                     0x02
#define CR0_BS2H_EN                     0x04
#define CR0_BH2S_EN                     0x08


//
// Bits in the CR3 register
//
#define CR3_FORSRST                     0x02
#define CR3_SFRST_DONE                  0x80


//
// Bits in the DCR0 register
//
#define DCR0_PS2H_GO                    0x01
#define DCR0_PH2S_GO                    0x02
#define DCR0_BS2H_GO                    0x04
#define DCR0_BH2S_GO                    0x08


//
// Bits in the ISR0 register(ISR0_OFF)
//
#define ISR_STATUS_ALL                  0xFFFFFFFF
#define ISR0_PTX0I                      0x01
#define ISR0_PTX1I                      0x02
#define ISR0_PTX2I                      0x04
#define ISR0_PRX0I                      0x10
#define ISR0_PRX1I                      0x20
#define ISR0_PRX2I                      0x40
#define ISR0_ALL                        (ISR0_PTX0I | ISR0_PTX1I | ISR0_PTX2I | ISR0_PRX0I | ISR0_PRX1I | ISR0_PRX2I)


//
// Bits in the ISR1 register(ISR1_OFF)
//
#define ISR1_BWR0I                      0x01
#define ISR1_BWR1I                      0x02
#define ISR1_BWR2I                      0x04
#define ISR1_BRD0I                      0x10
#define ISR1_BRD1I                      0x20
#define ISR1_BRD2I                      0x40
#define ISR1_ALL                        (ISR1_BWR0I | ISR1_BWR1I | ISR1_BWR2I | ISR1_BRD0I | ISR1_BRD1I | ISR1_BRD2I)


//
// Bits in the ISR2 register(ISR2_OFF)
//
#define ISR2_BSE0I                      0x01
#define ISR2_BSE1I                      0x02
#define ISR2_BSE2I                      0x04
#define ISR2_BSE3I                      0x08
#define ISR2_UDPI                       0x80
#define ISR2_ALL                        (ISR2_BSE0I | ISR2_BSE1I | ISR2_BSE2I | ISR2_BSE3I | ISR2_UDPI)


//
// Bits in the ISR3 register(ISR3_OFF)
//
#define ISR3_ISR0_STATUS                0x10
#define ISR3_ISR1_STATUS                0x20
#define ISR3_ISR2_STATUS                0x40
#define ISR3_SWI                        0x80
#define ISR3_PCI_ALL                    0x70
#define ISR3_ALL                        (ISR3_PCI_ALL | ISR3_SWI)


//
// Bits in the CFG0 register(PGS_SIZE_OFF)
//
#define CFG0_TD_PGS_128B                0x01
#define CFG0_RD_PGS_128B                0x02

/*---------------------  Export Types  ------------------------------*/

/*---------------------  Export Macros  -----------------------------*/

/*---------------------  Export Classes  ----------------------------*/

/*---------------------  Export Variables  --------------------------*/

/*---------------------  Export Functions  --------------------------*/




#endif /* __SWITCH_H__ */