switch.h

vt6528芯片交换机API函数和文档运行程序

#define EGRS_TAG_RULE_TBL_DISABLE       0x80000000


//--------------------------------------
// 0200H PHY Control
//--------------------------------------

//
// Bits in the PHYCTL_CMD register
//
#define PHY_CMD_WRITE                   0x01
#define PHY_CMD_READ                    0x02
#define PHY_CMD_DIS_AUTO                0x04
#define PHY_CMD_EN_AUTO                 0x08


//
// Bits in the PHYCTL_STATUS_RD_DATA register
//
#define PHY_STATUS_BUSY                 0x01
#define PHY_STATUS_READ_ERR             0x02
#define PHY_STATUS_AUTOPOLL             0x04


//
// Bits in the PHYCTL_OPER_CFG register
//
#define PORT_ABL_ENABLE                 0x03
#define PORT_ABL_FULL_DPX               0x04
#define PORT_ABL_SPD10                  0x00
#define PORT_ABL_SPD100                 0x20
#define PORT_ABL_SPD1000                0x40


//
// Bits in the PHYCTL_PORT24_TBI_MODE register
//
#define TBI_STATUS_LINK_SYNC            0x01
#define TBI_STATUS_AUTO_NEGO_OK         0x02
#define TBI_STATUS_LINK_PARTNER_1G      0x04
#define TBI_STATUS_AUTO_NEGO_BYPASS     0x08
#define MODULE_CARD_PRESENT             0x10
#define MODULE_CARD_STATUS_CHANGE       0x20


//
// Bits in the PHYCTL_PORT24_MODE_CFG register
//
#define MODE_CFG_TBI                    0x01
#define MODE_CFG_TBI_ABL_NWAY           0x02
#define MODE_CFG_TBI_LNK_DOWN           0x08
#define MODE_CFG_STRAP_OVERRIDE         0x20


//
// Bits in the PHYCTL_DEFAULT_NWAY_CFG register
//
#define DEFAULT_NWAY_CFG_SPD100_FULL    0x01


//--------------------------------------
// 0300H Forwarding Table Control
//--------------------------------------

//
// Bits in the FWDCTL_TBL_CFG register
//
#define FWD_TBL_INTERNAL_VLAN_0         0x00
#define FWD_TBL_INTERNAL_VLAN_32        0x01
#define FWD_TBL_INTERNAL_VLAN_64        0x02
#define FWD_TBL_INTERNAL_VLAN_128       0x03


//
// Bits in the FWDCTL_TBL_HASH register
//
#define FWD_TBL_HASH_ALG_DIRECT         0x01


//
// Bits in the FWDCTL_AUTO_AGE_CYCLE_TIME register
//
#define AUTO_AGE_CYCLE_TIME_MASK        0x0003FFFF


//
// Bits in the FWDCTL_AUTO_AGE_CFG register
//
#define AUTO_AGE_EN                     0x01
#define AUTO_AGE_UNIT_100US             0x02


//
// Bits in the FWDCTL_CTRL_PKT_FWD_CFG register
//
#define FWD_CFG_BPDU_TO_ALL_NOT_CPU     0x0000
#define FWD_CFG_BPDU_TO_ONLY_CPU        0x0003
#define FWD_CFG_LACP_DROP               0x0008
#define FWD_CFG_LACP_TO_ONLY_CPU        0x000C
#define FWD_CFG_8021X_TO_ALL_NOT_CPU    0x0000
#define FWD_CFG_8021X_TO_ONLY_CPU       0x0030
#define FWD_CFG_GMRP_TO_ALL_NOT_CPU     0x0000
#define FWD_CFG_GMRP_TO_ONLY_CPU        0x0300
#define FWD_CFG_GVRP_TO_ALL_NOT_CPU     0x0000
#define FWD_CFG_GVRP_TO_ONLY_CPU        0x0C00


//
// Bits in the FWDCTL_ARP_CFG register
//
#define ARP_CFG_REQ_TO_CPU              0x01


//
// Bits in the FWDCTL_IP_CAP_CFG register
//
#define CAP_CFG_IGMP_MSK                0x000C
#define CAP_CFG_IGMP_TO_ALL_AND_CPU     0x0004

//
// Bits in the FWDCTL_IP_MCAST_CFG register
//
#define IP_MCAST_CFG_USE_DMAC           0x04


//
// Bits in the FWDCTL_VLAN_CFG register
//
#define VLAN_CFG_VLAN_EN                0x01
#define VLAN_CFG_PER_VLAN_CPU_FBDPM_EN  0x02


//
// Bits in the FWDCTL_UCAST_FLOOD_DPM register
//
#define BIT_MASK_PORT_ALL               0x03FFFFFF


//
// Bits in the FWDCTL_SNIFF_CFG register
//
#define SNIFF_CFG_PORT_ID_BIT_OFST      8


//
// Bits in the FWDCTL_SNIFF_MODE register
//
#define SNIFF_MODE_DISABLE              0x00
#define SNIFF_MODE_INGRS                0x01
#define SNIFF_MODE_EGRS                 0x02
#define SNIFF_MODE_INGRS_EGRS           0x03


//
// Bits in the FWDCTL_L2P_MIRROR_PORT_CFG register
//
#define L2P_MIRROR_EN                   0x20
#define L2P_MIRROR_PORT_MSK             0x1F

//
// Bits in the FWDCTL_PRIORITY_RAISED register
//
#define PRIORITY_BPDU                   0x08


//
// Bits in the FWDCTL_LEARN_EN register
//
#define LEARN_EN_ALL_PORT               0x1FFFFFF


//
// Bits in the FWDCTL_GBL_SECURITY_CFG register
//
#define GBL_SECU_SRC_INCON_NOT_CARE     0x00
#define GBL_SECU_SRC_INCON_STATIC       0x01
#define GBL_SECU_SRC_INCON_DYNAMIC      0x02
#define GBL_SECU_SRC_INCON_BOTH         0x03
#define GBL_SECU_BMCST_DETECT           0x04
#define GBL_SECU_SMACSIP_DETECT         0x08
#define GBL_SECU_SV_FWD                 0x0300
#define GBL_SECU_LOG_SV_SMAC            0x0400
#define GBL_SECU_CTRL_PKT               0x010000


//
// Bits in the FWDCTL_LOAD_BALANCE_ALG register
//
#define LOAD_BALANCE_ALG_DMAC           0x01
#define LOAD_BALANCE_ALG_SMAC           0x02
#define LOAD_BALANCE_ALG_INGRS_PORTID   0x04
#define LOAD_BALANCE_ALG_DIP_ADDR       0x08
#define LOAD_BALANCE_ALG_SIP_ADDR       0x10
#define LOAD_BALANCE_ALG_TCP_UDP_DPORT  0x20
#define LOAD_BALANCE_ALG_TCP_UDP_SPORT  0x40
#define LOAD_BALANCE_ALG_DIRECT         0x80

//
// Bits in the FWDCTL_SCAN_CMD_MV_FRM_FID register
//
#define FWDCTL_SCAN_CMD_FID_EN          0x2000
#define FWDCTL_SCAN_CMD_PID_EN          0x40


//
// Bits in the FWDCTL_SCAN_CMD register
//
#define SCAN_CMD_SEARCH                 0x00
#define SCAN_CMD_SELECT_CLR             0x01
#define SCAN_CMD_MODIFY                 0x02



//
// Bits in the FWDCTL_SCAN_STATUS register
//
#define SCAN_STATUS_BUSY                0x01


//
// Bits in the FWDCTL_LOG_CTRL register
//
#define LOG_CTRL_LOG_TBL_ENABLE         0x01
#define LOG_CTRL_PAUSE                  0x02
#define LOG_CTRL_INTRQ_THR16            0x00
#define LOG_CTRL_INTRQ_THR64            0x04
#define LOG_CTRL_INTRQ_THR256           0x08
#define LOG_CTRL_INTRQ_THR1024          0x0C


//
// Bits in the FWDCTL_STP_STATE_PORT0_15 register
//
#define STP_STATE_DISABLED              0x00
#define STP_STATE_BLOCKING              0x01
#define STP_STATE_LEARNING              0x02
#define STP_STATE_FORWARDING            0x03
#define STP_STATE_LISTENING             0x04    //not implement in hardware, so must cover by software function


//--------------------------------------
// 0400H Initialization Control
//--------------------------------------

//
// Bits in the INITCTL_CHIP_STRAP_CFG register
//
#define CHIP_CFG_GIGA0_GMII             0x0100  // if this bit off, then it's TBI mode
#define CHIP_CFG_GIGA1_GMII             0x0080  // if this bit off, then it's TBI mode


//
// Bits in the INITCTL_EEP_CMD register
//
#define EEP_CMD_DEV_ID_MSK              0x0E
#define EEP_CMD_WR                      0xA0
#define EEP_CMD_RD                      0xA1


//
// Bits in the INITCTL_EEP_STATUS register
//
#define EEP_STATUS_BUSY                 0x01
#define EEP_STATUS_OK                   0x02
#define EEP_STATUS_ERR                  0x04
#define EEP_STATUS_INIT_ERR             0x08


//
// Bits in the INITCTL_BASIC_FUNC_CFG register
//
#define FUNC_CFG_COL_RETRY_EVER         0x00
#define FUNC_CFG_COL_RETRY_16           0x01
#define FUNC_CFG_COL_RETRY_32           0x02
#define FUNC_CFG_COL_RETRY_48           0x03
#define FUNC_CFG_DEADLOCK_PREVENTION_EN 0x8000
#define FUNC_CFG_DEADLOCK_DISREGARD_FC  (0x1<<21)

#define FUNC_CFG_DEADLOCK_RELIEF_EN     0x80
#define FUNC_CFG_FC_VIO_EN              0x10


//
// Bits in the INITCTL_LED_OUT_CFG register
//
#define FUNC_CFG_BSF_LED                0x0100


//
// Bits in the INITCTL_TMAC_RESET register
//
#define TMAC_RESET_PORT0_23             0x01
#define TMAC_RESET_PORT24               0x02
#define TMAC_RESET_PORT25               0x04


//
// Bits in the INITCTL_MIB_EN register
//
#define MIB_ENABLE                      0x01


//
// Bits in the INITCTL_POWER_UP_STATUS register
//
#define POWER_UP_STATUS_RESET_OK        0x01
#define POWER_UP_STATUS_BIST_OK         0x08


//
// Bits in the INITCTL_POWER_UP_CMD register
//
#define POWER_UP_WARM_BOOT              0x01
#define POWER_UP_COLD_BOOT              0x02


//--------------------------------------
// 0500H Queue Control
//--------------------------------------

//
// Bits in the QUECTL_OUT_SCHE_MODE register
//
#define SCHE_SEL_FCFS                   0x00
#define SCHE_SEL_SP                     0x01
#define SCHE_SEL_WRR                    0x02


//
// Bits in the QUECTL_OUT_WEIGHT register
//
#define OUT_WEIGHT_8_4_2_1              0x8421      // 1000_0100_0010_0001 b
#define OUT_WEIGHT_15_7_3_1             0xF731      // 1111_0111_0011_0001 b
#define OUT_WEIGHT_15_10_5_1            0xFA51      // 1111_1010_0101_0001 b


//
// Bits in the QUECTL_DEQUE_HOLD register
//
#define DEQUE_HOLD_CPU                  0x04