switch.h

vt6528芯片交换机API函数和文档运行程序

#define BUFCTL_FREE_MEM_CNT         BUFCTL_BASE_ADDR + 0x00
#define BUFCTL_INIT                 BUFCTL_BASE_ADDR + 0x04

#define BUFCTL_BUF_CFG              BUFCTL_BASE_ADDR + 0x40
#define BUFCTL_FREE_LNK_LST_LEN0    BUFCTL_BASE_ADDR + 0x48
#define BUFCTL_FREE_LNK_LST_LEN1    BUFCTL_BASE_ADDR + 0x4A
#define BUFCTL_FREE_LNK_LST_LEN2    BUFCTL_BASE_ADDR + 0x4C
#define BUFCTL_FREE_LNK_LST_LEN3    BUFCTL_BASE_ADDR + 0x4E

#define BUFCTL_FREE_LNK_LST0_HEAD   BUFCTL_BASE_ADDR + 0x50
#define BUFCTL_FREE_LNK_LST0_TAIL   BUFCTL_BASE_ADDR + 0x52
#define BUFCTL_FREE_LNK_LST1_HEAD   BUFCTL_BASE_ADDR + 0x54
#define BUFCTL_FREE_LNK_LST1_TAIL   BUFCTL_BASE_ADDR + 0x56
#define BUFCTL_FREE_LNK_LST2_HEAD   BUFCTL_BASE_ADDR + 0x58
#define BUFCTL_FREE_LNK_LST2_TAIL   BUFCTL_BASE_ADDR + 0x5A
#define BUFCTL_FREE_LNK_LST3_HEAD   BUFCTL_BASE_ADDR + 0x5C
#define BUFCTL_FREE_LNK_LST3_TAIL   BUFCTL_BASE_ADDR + 0x5E

#define BUFCTL_PREFETCH_BUF0        BUFCTL_BASE_ADDR + 0x60
#define BUFCTL_PREFETCH_BUF1        BUFCTL_BASE_ADDR + 0x62
#define BUFCTL_PREFETCH_BUF2        BUFCTL_BASE_ADDR + 0x64
#define BUFCTL_PREFETCH_BUF3        BUFCTL_BASE_ADDR + 0x66
#define BUFCTL_PREFETCH_BUF4        BUFCTL_BASE_ADDR + 0x68
#define BUFCTL_PREFETCH_BUF5        BUFCTL_BASE_ADDR + 0x6A
#define BUFCTL_PREFETCH_BUF6        BUFCTL_BASE_ADDR + 0x6C
#define BUFCTL_PREFETCH_BUF7        BUFCTL_BASE_ADDR + 0x6E


// Resource Management
#define RESMGMT_BASE_ADDR            0x0700

#define RESMGMT_MANAGER_CFG         RESMGMT_BASE_ADDR + 0x00
#define RESMGMT_PORT24_25_CFG       RESMGMT_BASE_ADDR + 0x01
#define RESMGMT_BSF_INDICAT         RESMGMT_BASE_ADDR + 0x04
#define RESMGMT_INGRS_RATE_LIMIT1   RESMGMT_BASE_ADDR + 0x08
#define RESMGMT_INGRS_RATE_LIMIT2   RESMGMT_BASE_ADDR + 0x0C

#define RESMGMT_LEAVE_SYS_XOFF_THR  RESMGMT_BASE_ADDR + 0x10
#define RESMGMT_ENTER_SYS_XOFF_THR  RESMGMT_BASE_ADDR + 0x12
#define RESMGMT_LEAVE_ALL_XOFF_THR  RESMGMT_BASE_ADDR + 0x14
#define RESMGMT_ENTER_ALL_XOFF_THR  RESMGMT_BASE_ADDR + 0x16
#define RESMGMT_ENTER_CONG_THR1     RESMGMT_BASE_ADDR + 0x18
#define RESMGMT_LEAVE_CONG_THR1     RESMGMT_BASE_ADDR + 0x1C
#define RESMGMT_THR1_ATTR           RESMGMT_BASE_ADDR + 0x1D

#define RESMGMT_ENTER_CONG_THR2     RESMGMT_BASE_ADDR + 0x20
#define RESMGMT_LEAVE_CONG_THR2     RESMGMT_BASE_ADDR + 0x24
#define RESMGMT_CPU_ENTER_CONG_THR  RESMGMT_BASE_ADDR + 0x28
#define RESMGMT_CPU_LEAVE_CONG_THR  RESMGMT_BASE_ADDR + 0x2C
#define RESMGMT_CPU_THR_ATTR        RESMGMT_BASE_ADDR + 0x2D

#define RESMGMT_INGRS_BUF_USAGE_THR RESMGMT_BASE_ADDR + 0x30
#define RESMGMT_CPU_BUF_USAGE_THR   RESMGMT_BASE_ADDR + 0x34
#define RESMGMT_LIGHTLY_LOADED_THR  RESMGMT_BASE_ADDR + 0x38
#define RESMGMT_BP_SUPP_EN          RESMGMT_BASE_ADDR + 0x3C

#define RESMGMT_PKT_RATE_LIMIT_CFG1 RESMGMT_BASE_ADDR + 0x40
#define RESMGMT_PKT_RATE_LIMIT_CFG2 RESMGMT_BASE_ADDR + 0x41

#define RESMGMT_ID                  RESMGMT_BASE_ADDR + 0x80
#define RESMGMT_CONG_MAKER          RESMGMT_BASE_ADDR + 0x84
#define RESMGMT_SEG_LEN             RESMGMT_BASE_ADDR + 0x88
#define RESMGMT_SYS_XOFF_WIN        RESMGMT_BASE_ADDR + 0x8C

#define RESMGMT_EGRS_CONG_WIN       RESMGMT_BASE_ADDR + 0x90
#define RESMGMT_INGRS_DROP_WIN      RESMGMT_BASE_ADDR + 0x94


// SRAM BIST Control
#define SRAMCTL_BASE_ADDR            0x0800

#define SRAMCTL_GBL_BIST_CYCLE      SRAMCTL_BASE_ADDR + 0x00
#define SRAMCTL_GBL_BIST_CFG        SRAMCTL_BASE_ADDR + 0x03
#define SRAMCTL_NON_REPAIR_STATUS   SRAMCTL_BASE_ADDR + 0x04
#define SRAMCTL_MOSYS_BIST_CFG      SRAMCTL_BASE_ADDR + 0x08
#define SRAMCTL_MOSYS_BIST_STATUS   SRAMCTL_BASE_ADDR + 0x0C

#define SRAMCTL_MOSYS_MEM_ERR0      SRAMCTL_BASE_ADDR + 0x10
#define SRAMCTL_MOSYS_MEM_ERR1      SRAMCTL_BASE_ADDR + 0x12
#define SRAMCTL_MOSYS_MEM_ERR2      SRAMCTL_BASE_ADDR + 0x14
#define SRAMCTL_MOSYS_MEM_ERR3      SRAMCTL_BASE_ADDR + 0x16
#define SRAMCTL_MOSYS_MEM_ERR4      SRAMCTL_BASE_ADDR + 0x18
#define SRAMCTL_MOSYS_MEM_ERR5      SRAMCTL_BASE_ADDR + 0x1A
#define SRAMCTL_MOSYS_BIST_ERR_NUM  SRAMCTL_BASE_ADDR + 0x1C

#define SRAMCTL_MOSYS_BIST_ERR_VEC0 SRAMCTL_BASE_ADDR + 0x20
#define SRAMCTL_MOSYS_BIST_ERR_VEC1 SRAMCTL_BASE_ADDR + 0x24
#define SRAMCTL_MOSYS_BIST_ERR_VEC2 SRAMCTL_BASE_ADDR + 0x28
#define SRAMCTL_MOSYS_BIST_ERR_VEC3 SRAMCTL_BASE_ADDR + 0x2C

#define SRAMCTL_CAM_BIST_CFG        SRAMCTL_BASE_ADDR + 0x30
#define SRAMCTL_CAM_BIST_STATUS     SRAMCTL_BASE_ADDR + 0x34
#define SRAMCTL_CAM_BIST_ERR_NUM    SRAMCTL_BASE_ADDR + 0x38
#define SRAMCTL_CAM_BIST_ERR_VEC0   SRAMCTL_BASE_ADDR + 0x3C

#define SRAMCTL_CAM_BIST_ERR_VEC1   SRAMCTL_BASE_ADDR + 0x40
#define SRAMCTL_CAM_BIST_ERR_VEC2   SRAMCTL_BASE_ADDR + 0x44
#define SRAMCTL_CAM_BIST_ERR_VEC3   SRAMCTL_BASE_ADDR + 0x48
#define SRAMCTL_CAM_BIST_ERR_VEC4   SRAMCTL_BASE_ADDR + 0x4C

#define SRAMCTL_CAM_BIST_ERR_VEC5   SRAMCTL_BASE_ADDR + 0x50
#define SRAMCTL_CAM_BIST_ERR_VEC6   SRAMCTL_BASE_ADDR + 0x54
#define SRAMCTL_CAM_BIST_ERR_VEC7   SRAMCTL_BASE_ADDR + 0x58
#define SRAMCTL_ATS_BIST_CFG        SRAMCTL_BASE_ADDR + 0x5C

#define SRAMCTL_ATS_BIST_STATUS     SRAMCTL_BASE_ADDR + 0x60
#define SRAMCTL_ATS_BIST_ERR_VEC0   SRAMCTL_BASE_ADDR + 0x64
#define SRAMCTL_ATS_BIST_ERR_VEC1   SRAMCTL_BASE_ADDR + 0x68
#define SRAMCTL_ATS_BIST_ERR_VEC2   SRAMCTL_BASE_ADDR + 0x6C


// Advanced Forwarding Table Control
#define ADVFWD_BASE_ADDR            0x0C00

#define PRIO_ADJ_PROF_OFFSET        0x04

#define ADVFWD_PRIO_ADJ_PROF0       ADVFWD_BASE_ADDR + 0x00
#define ADVFWD_PRIO_ADJ_PROF1       ADVFWD_BASE_ADDR + 0x04
#define ADVFWD_PRIO_ADJ_PROF2       ADVFWD_BASE_ADDR + 0x08
#define ADVFWD_PRIO_ADJ_PROF3       ADVFWD_BASE_ADDR + 0x0C

#define ADVFWD_SCOPE0_OPT           ADVFWD_BASE_ADDR + 0x20
#define ADVFWD_SCOPE1_OPT           ADVFWD_BASE_ADDR + 0x21
#define ADVFWD_SCOPE2_OPT           ADVFWD_BASE_ADDR + 0x22
#define ADVFWD_SCOPE3_OPT           ADVFWD_BASE_ADDR + 0x23

#define ADVFWD_SCOPE0               ADVFWD_BASE_ADDR + 0x40
#define ADVFWD_SCOPE1               ADVFWD_BASE_ADDR + 0x44
#define ADVFWD_SCOPE2               ADVFWD_BASE_ADDR + 0x48
#define ADVFWD_SCOPE3               ADVFWD_BASE_ADDR + 0x4C


// Port 0-25 Configuration
#define PORTCFG_BASE_ADDR           0x1000
#define PORTCFG_PORT_OFFSET         0x40


#define PORTCFG_TRUNK_CRITERIA_BASE PORTCFG_BASE_ADDR + 0x00
#define PORTCFG_TRUNK_CFG_BASE      PORTCFG_BASE_ADDR + 0x01
#define PORTCFG_VLAN_CFG_BASE       PORTCFG_BASE_ADDR + 0x04
#define PORTCFG_VLAN_MODE_BASE      PORTCFG_BASE_ADDR + 0x07
#define PORTCFG_PRIO_CFG_BASE       PORTCFG_BASE_ADDR + 0x08
#define PORTCFG_PRIO_ADJ_BASE       PORTCFG_BASE_ADDR + 0x09
#define PORTCFG_INGRS_FLTR_BASE     PORTCFG_BASE_ADDR + 0x0C
#define PORTCFG_FWD_SCOPE_ID_BASE   PORTCFG_BASE_ADDR + 0x0D
#define PORTCFG_TUNNEL_CFG_BASE     PORTCFG_BASE_ADDR + 0x0E
#define PORTCFG_BSF_CFG_BASE        PORTCFG_BASE_ADDR + 0x0F

#define PORTCFG_INGRS_RATE_CFG_BASE PORTCFG_BASE_ADDR + 0x10
#define PORTCFG_EGRS_RATE_OVHD_BASE PORTCFG_BASE_ADDR + 0x14
#define PORTCFG_EGRS_RATE_CFG_BASE  PORTCFG_BASE_ADDR + 0x15


// Port 0-25 IO Control Diagnostic
#define IOCTLDIAG_BASE_ADDR         0x1800
#define IOCTLDIAG_PORT_OFFSET       0x20


#define IOCTLDIAG_ALLOC_ADDR_BASE   IOCTLDIAG_BASE_ADDR + 0x00
#define IOCTLDIAG_LATCH_ADDR_BASE   IOCTLDIAG_BASE_ADDR + 0x02
#define IOCTLDIAG_GRNT_ADDR0_BASE   IOCTLDIAG_BASE_ADDR + 0x04
#define IOCTLDIAG_GRNT_ADDR1_BASE   IOCTLDIAG_BASE_ADDR + 0x06
#define IOCTLDIAG_GRNT_ADDR2_BASE   IOCTLDIAG_BASE_ADDR + 0x08
#define IOCTLDIAG_DEQUE_ADDR0_BASE  IOCTLDIAG_BASE_ADDR + 0x0C
#define IOCTLDIAG_DEQUE_ADDR1_BASE  IOCTLDIAG_BASE_ADDR + 0x0E




//--------------------------------------
// 0000H CPU Interface Control
//--------------------------------------

//
// Bits in the CPUIF_IRQ_STATUS register
//
#define IRQ_STATUS_INIT_OK              0x0001
#define IRQ_STATUS_LINK_CHG             0x0002
#define IRQ_STATUS_PKT_RX               0x0004
#define IRQ_STATUS_PKT_TX               0x0008
#define IRQ_STATUS_LOG_OVER_THR         0x0010
#define IRQ_STATUS_MEM_DMA_DONE         0x0020
#define IRQ_STATUS_WRPKT_DMA_DONE       0x0040
#define IRQ_STATUS_RDPKT_DMA_DONE       0x0080
#define IRQ_STATUS_LOG_FULL             0x0100
#define IRQ_STATUS_BUF_STARVATION       0x0200
#define IRQ_STATUS_BSF                  0x0400
#define IRQ_STATUS_ALL                  0x07FF


//
// Bits in the CPUIF_HOSTIF_CFG register
//
#define HOSTIF_INTRQ_MODE_LOW           0x01
#define HOSTIF_BUS_ENDIAN_BIG           0x02
#define HOSTIF_TRANS_DMA                0x04
#define HOSTIF_BUS_WIDTH16              0x10
#define HOSTIF_MASTER_MODE              0x20


//
// Bits in the CPUIF_REQ_CFG register
//
#define CPUIF_REQ0_EN                   0x01
#define CPUIF_REQ1_EN                   0x02
#define CPUIF_REQ2_EN                   0x04
#define CPUIF_REQ_EN_ALL                0x07


//
// Bits in the CPUIF_BYTE_SWAP_CFG register
//
#define BYTE_SWAP_ENABLE                0x01


//
// Bits in the CPUIF_WR_BYTE_EN register
//
#define WR_BYTE_EN_ALL_BITS             0xFFFF


//
// Bits in the CPUIF_MEM_CMD register
//
#define MEM_CMD_READ                    0x01
#define MEM_CMD_WRITE                   0x02
#define MEM_CMD_READ_INC_ADDR           0x04
#define MEM_CMD_WRITE_INC_ADDR          0x08
#define MEM_CMD_BCAM_CMP                0x10
#define MEM_CMD_TCAM_CMP                0x20


//
// Bits in the CPUIF_MEM_STATUS register
//
#define MEM_STATUS_FAIL                 0x01
#define MEM_STATUS_BUSY                 0x02


//
// Bits in the CPUIF_CPU_PKT_CMD register
//
#define CPU_PKT_CMD_WR_PKT_START        0x01
#define CPU_PKT_CMD_WR_PKT_MIDDLE       0x02
#define CPU_PKT_CMD_WR_PKT_ABORT        0x03
#define CPU_PKT_CMD_WR_PKT_1_VALID      0x04
#define CPU_PKT_CMD_WR_PKT_2_VALID      0x05
#define CPU_PKT_CMD_WR_PKT_3_VALID      0x06
#define CPU_PKT_CMD_WR_PKT_4_VALID      0x07
#define CPU_PKT_CMD_RD_PKT_ABORT        0x08


//
// Bits in the CPUIF_DMA_ABT_POLICY register
//
#define DMA_ABT_PRIOR_MEM_WP_RP         0x00    // If set Memory>WP>RP, then set Reg0x004A=DMA_ABT_PRIOR_MEM_WP_RP; If want to check whether Memory>WP>RP, then check ( read(Reg0x004A) & DMA_ABT_PRIOR_MSK == DMA_ABT_PRIOR_MEM_WP_RP)
#define DMA_ABT_PRIOR_MEM_RP_WP         0x01
#define DMA_ABT_PRIOR_WP_MEM_RP         0x02
#define DMA_ABT_PRIOR_WP_RP_MEM         0x03
#define DMA_ABT_PRIOR_RP_MEM_WP         0x04
#define DMA_ABT_PRIOR_RP_WP_MEM         0x05
#define DMA_ABT_PRIOR_MSK               0x07    // get the bits value

#define DMA_ABT_POLICY_SP               0x00
#define DMA_ABT_POLICY_RR               0x08
#define DMA_ABT_POLICY_CPU              0x10
#define DMA_ABT_POLICY_MSK              0x18    // get the bits value


//
// Bits in the CPUIF_MEM_DMA_STATUS register
// Bits in the CPUIF_WR_PKT_DMA_STATUS register
// Bits in the CPUIF_RD_PKT_DMA_STATUS register
//
#define DMA_STATUS_FAIL                 0x01
#define DMA_STATUS_TRANS_OK             0x02


//
// Bits in the CPUIF_MEM_DMA_MODE register
// Bits in the CPUIF_WR_PKT_DMA_MODE register
// Bits in the CPUIF_RD_PKT_DMA_MODE register
//
#define DMA_MODE_DEMAND                 0x02
#define DMA_CH0                         0x00
#define DMA_CH1                         0x10
#define DMA_CH2                         0x20
#define DMA_CMD_RD                      0x40
#define DMA_CMD_WR                      0x00


//
// Bits in the CPUIF_MEM_DMA_CH_RDY register
// Bits in the CPUIF_WR_PKT_DMA_CH_RDY register
// Bits in the CPUIF_RD_PKT_DMA_CH_RDY register
//
#define DMA_CH_RDY                      0x01
#define DMA_ABORT                       0x02


//--------------------------------------
// 0100H CPU Port Control
//--------------------------------------

//
// Bits in the CPUPORT_CFG register
//
#define CPU_CFG_TX_ENABLE               0x01
#define CPU_CFG_RX_ENABLE               0x02
#define CPU_CFG_RX_TAG_REMOVE_EN        0x04


//
// Bits in the CPUPORT_OUTPUT_PORT_STATUS register
//
#define RD_PKT_RDY                      0x01
#define RD_PKT_PEND                     0x02
#define RD_PKT_TRANS_OK                 0x04
#define RD_PKT_TRANS_FAIL               0x08


//
// Bits in the CPUPORT_RD_PKT_ATTRIB register
//
#define RD_PKT_ATTRIB_PORTID_MSK        0x1F
#define RD_PKT_ATTRIB_REASON_SECURITY   0x00
#define RD_PKT_ATTRIB_REASON_NONSEC     0x20
#define RD_PKT_ATTRIB_TAGGED            0x80


//
// Bits in the CPUPORT_INPUT_PORT_STATUS register
//
#define WR_PKT_STATUS_RDY               0x01
#define WR_PKT_STATUS_TRANS_OK          0x02
#define WR_PKT_STATUS_TRANS_FAIL        0x04


//
// Bits in the CPUPORT_WR_PKT_EGRS_RULE register
//