switch.h

vt6528芯片交换机API函数和文档运行程序

/*
 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
 * All rights reserved.
 *
 * This software is copyrighted by and is the sole property of
 * VIA Networking Technologies, Inc. This software may only be used
 * in accordance with the corresponding license agreement. Any unauthorized
 * use, duplication, transmission, distribution, or disclosure of this
 * software is expressly forbidden.
 *
 * This software is provided by VIA Networking Technologies, Inc. "as is"
 * and any express or implied warranties, including, but not limited to, the
 * implied warranties of merchantability and fitness for a particular purpose
 * are disclaimed. In no event shall VIA Networking Technologies, Inc.
 * be liable for any direct, indirect, incidental, special, exemplary, or
 * consequential damages.
 *
 *
 * File:    switch.h
 *
 * Purpose: Switch hardware feature and register address definition
 *
 * Author:  Tevin Chen
 *
 * Date:    Jan 08, 2002
 *
 */


#ifndef __SWITCH_H__
#define __SWITCH_H__


/*---------------------  Export Definitions  ------------------------*/

//--------------------------------------
// Definition for SRAM
//--------------------------------------

#define SRAM_ENTRY_MAX_SIZE         16
#define SRAM_ENTRY_MAX_BIT_NUM      (SRAM_ENTRY_MAX_SIZE * 8)
#define SRAM_ENTRY_SIZE_4Byte       4
#define SRAM_ENTRY_SIZE_8Byte       8
#define SRAM_ENTRY_SIZE_16Byte      16

#define SHIFT_NUM_SIZE_4Byte        2
#define SHIFT_NUM_SIZE_8Byte        3
#define SHIFT_NUM_SIZE_16Byte       4


#define TCAM_ENTRY_NUM              (SRAM_TCAM_VALUE_SIZE / SRAM_ENTRY_SIZE_16Byte)
#define PMAC_SLOT_NUM               (SRAM_PMAC_TBL_SIZE / SRAM_ENTRY_SIZE_8Byte)
#define BCAM_ENTRY_NUM              (SRAM_SECOND_MAC_INDX_SIZE / SRAM_ENTRY_SIZE_16Byte)

//--------------------------------------
// Definition for SRAM: Base Address for Arbitrary Tables
//--------------------------------------

#define SRAM_PKT_BUF_TBL_SIZE               (0x80000)           //512 KB, 512K == 0x80000; 512KB = 512*8Kb = 4Mb
#define SRAM_PKTDESC_QUELNK_TBL_SIZE        (0x10000)           //64  KB, 64K  == 0x10000
#define SRAM_MIB_TBL_SIZE                   (0x00D00)           //3 KB + 256 B, 3 K + 256   == 0x00D00
#define SRAM_MAC_LOG_TBL_SIZE               (0x0C000)           //48  KB, 48K  == 0x0C000
#define SRAM_MAC_TBL_SIZE                   (0x10000)           //64  KB, 64K  == 0x10000
#define SRAM_PMAC_TBL_SIZE                  (0x10000)           //64  KB, 64K  == 0x10000
#define SRAM_VLAN_TBL_SIZE                  (0x10000)           //64  KB, 64K  == 0x10000
#define SRAM_SGMNT_LNK_SIZE                 (0x04000)           //16  KB, 16K  == 0x04000
#define SRAM_TCAM_VALUE_SIZE                (0x01000)           // 4  KB,  4K  == 0x01000
#define SRAM_TCAM_MASK_SIZE                 (0x01000)           // 4  KB,  4K  == 0x01000
#define SRAM_TCAM_VLD_SIZE                  (0x01000)           // 4  KB,  4K  == 0x01000
#define SRAM_SECOND_MAC_INDX_SIZE           (0x01000)           // 4  KB,  4K  == 0x01000
#define SRAM_RULE_ACT_CODE_SIZE             (0x00800)           // 2  KB,  2K  == 0x00800
#define SRAM_SECOND_MAC_TBL_SIZE            (0x00400)           // 1  KB,  1K  == 0x00400
#define SRAM_RULE_CNTR_TBL_SIZE             (0x01000)           // 4  KB,  4K  == 0x01000
#define SRAM_PTMSK_TBL_SIZE                 (0x01000)           // 4  KB,  4K  == 0x01000
#define SRAM_STP_TBL_SIZE                   (0x00200)           //512  B, 512  == 0x00200
#define SRAM_TOSDSCP_1P_MAP_TBL_SIZE        (0x00020)           //32   B,  32  == 0x00020
#define SRAM_MCAST_CNTR_TBL_SIZE            (0x04000)           //16  KB, 16K  == 0x04000

#define SRAM_PKT_BUF_TBL_BASE_ADDR          (0x00000)               // 4Mb packet buffer base address
#define SRAM_PKTDESC_QUELNK_TBL_BASE_ADDR   (0x80000)               // Packet descriptor + queue link base address
#define SRAM_MIB_TBL_BASE_ADDR              (0x90000)               // MIB counters table base address
#define SRAM_MAC_LOG_TBL_BASE_ADDR          (0x94000)               // MAC address table change log base address
#define SRAM_PMAC_TBL_BASE_ADDR             (0xA0000)               // MAC table base address
#define SRAM_VLAN_TBL_BASE_ADDR             (0xB0000)               // VLAN table base address
#define SRAM_SGMNT_LNK_BASE_ADDR            (0xC8000)               // Segment link base address
#define SRAM_SGMNT_LNK_END_ADDR             (SRAM_SGMNT_LNK_BASE_ADDR + SRAM_SGMNT_LNK_SIZE - 1)
#define SRAM_TCAM_VALUE_BASE_ADDR           (0xD0000)               // L2+ classification rule table base address, TCAM value array
#define SRAM_TCAM_MASK_BASE_ADDR            (0xD1000)               // L2+ classification rule table base address, TCAM mask array
#define SRAM_TCAM_VLD_BASE_ADDR             (0xD2000)               // L2+ classification rule table base address, TCAM valid array
#define SRAM_SECOND_MAC_INDX_BASE_ADDR      (0xD8000)               // Secondary MAC address table index, BCAM base address
#define SRAM_RULE_ACT_CODE_BASE_ADDR        (0xDA000)               // L2+ rule action code table base address
#define SRAM_SECOND_MAC_TBL_BASE_ADDR       (0xDA800)               // Secondary MAC address table base address
#define SRAM_SECOND_MAC_TBL_END_ADDR        (SRAM_SECOND_MAC_TBL_BASE_ADDR + SRAM_SECOND_MAC_TBL_SIZE - 1)
#define SRAM_RULE_CNTR_TBL_BASE_ADDR        (0xDC000)               // L2+ rule counters table base address
#define SRAM_PTMSK_TBL_BASE_ADDR            (0xE0000)               // Multicast port mask base address
#define SRAM_PTMSK_TBL_END_ADDR             (SRAM_PTMSK_TBL_BASE_ADDR + SRAM_PTMSK_TBL_SIZE - 1)
#define SRAM_STP_TBL_BASE_ADDR              (0xE1000)               // Spanning Trees states base address
#define SRAM_TOSDSCP_1P_MAP_TBL_BASE_ADDR   (0xE1200)               // ToS/DSCP-to-802.1p mapping table base address
#define SRAM_MCAST_CNTR_TBL_BASE_ADDR       (0xE4000)               // Multicast counters base address
#define SRAM_MCAST_CNTR_TBL_END_ADDR        (SRAM_MCAST_CNTR_TBL_BASE_ADDR + SRAM_MCAST_CNTR_TBL_SIZE - 1)


//--------------------------------------
// Definition for Switch Registers
//--------------------------------------

// 0000H CPU Interface Control
// 0100H CPU Port Control
// 0200H PHY Control
// 0300H Forwarding Table Control
// 0400H Initialization Control
// 0500H Queue Control
// 0600H Buffer Control
// 0700H Resource Management
// 0800H SRAM BIST Control
// 0C00H Advanced Forwarding Table Control
// 1000H-1640H Port 0-25 Configuration
// 1800H-1B20H Port 0-25 IO Control Diagnostic


// CPU Interface Control
#define CPUIF_BASE_ADDR             0x0000

#define CPUIF_IRQ_STATUS            CPUIF_BASE_ADDR + 0x00
#define CPUIF_IRQ_MASK              CPUIF_BASE_ADDR + 0x04
#define CPUIF_HOSTIF_CFG            CPUIF_BASE_ADDR + 0x08
#define CPUIF_REQ_CFG               CPUIF_BASE_ADDR + 0x09
#define CPUIF_BYTE_SWAP_CFG         CPUIF_BASE_ADDR + 0x0C

#define CPUIF_MEM_ADDR              CPUIF_BASE_ADDR + 0x10
#define CPUIF_WR_BYTE_EN            CPUIF_BASE_ADDR + 0x14
#define CPUIF_MEM_CMD               CPUIF_BASE_ADDR + 0x18
#define CPUIF_MEM_STATUS            CPUIF_BASE_ADDR + 0x1C
#define CPUIF_MEM_STATUS_ADDR       CPUIF_BASE_ADDR + 0x1E

#define CPUIF_MEM_DATA0             CPUIF_BASE_ADDR + 0x20
#define CPUIF_MEM_DATA1             CPUIF_BASE_ADDR + 0x24
#define CPUIF_MEM_DATA2             CPUIF_BASE_ADDR + 0x28
#define CPUIF_MEM_DATA3             CPUIF_BASE_ADDR + 0x2C

#define CPUIF_CPU_PKT_CMD           CPUIF_BASE_ADDR + 0x40
#define CPUIF_DMA_ABT_MEM_WRR_CNT   CPUIF_BASE_ADDR + 0x44
#define CPUIF_DMA_ABT_WP_WRR_CNT    CPUIF_BASE_ADDR + 0x46
#define CPUIF_DMA_ABT_RP_WRR_CNT    CPUIF_BASE_ADDR + 0x48
#define CPUIF_DMA_ABT_POLICY        CPUIF_BASE_ADDR + 0x4A
#define CPUIF_DMA_CONTROLLER        CPUIF_BASE_ADDR + 0x4C

#define CPUIF_MEM_DMA_STATUS        CPUIF_BASE_ADDR + 0x50
#define CPUIF_MEM_DMA_ADDR          CPUIF_BASE_ADDR + 0x54
#define CPUIF_MEM_DMA_TRANS_CNT     CPUIF_BASE_ADDR + 0x58
#define CPUIF_MEM_DMA_MODE          CPUIF_BASE_ADDR + 0x5A
#define CPUIF_MEM_DMA_CH_RDY        CPUIF_BASE_ADDR + 0x5B
#define CPUIF_WR_PKT_DMA_STATUS     CPUIF_BASE_ADDR + 0x5C

#define CPUIF_WR_PKT_DMA_TRANS_CNT  CPUIF_BASE_ADDR + 0x60
#define CPUIF_WR_PKT_DMA_MODE       CPUIF_BASE_ADDR + 0x62
#define CPUIF_WR_PKT_DMA_CH_RDY     CPUIF_BASE_ADDR + 0x63
#define CPUIF_RD_PKT_DMA_STATUS     CPUIF_BASE_ADDR + 0x64
#define CPUIF_RD_PKT_DMA_TRANS_CNT  CPUIF_BASE_ADDR + 0x68
#define CPUIF_RD_PKT_DMA_MODE       CPUIF_BASE_ADDR + 0x6A
#define CPUIF_RD_PKT_DMA_CH_RDY     CPUIF_BASE_ADDR + 0x6B
#define CPUIF_SLAVE_RW_PKT_PORT     CPUIF_BASE_ADDR + 0x80


// CPU Port Control
#define CPUPORT_BASE_ADDR           0x0100

#define CPUPORT_CFG                 CPUPORT_BASE_ADDR + 0x00
#define CPUPORT_OUTPUT_PORT_STATUS  CPUPORT_BASE_ADDR + 0x04
#define CPUPORT_RD_PKT_BYTE_CNT     CPUPORT_BASE_ADDR + 0x08
#define CPUPORT_RD_PKT_ATTRIB       CPUPORT_BASE_ADDR + 0x0A
#define CPUPORT_RD_PKT_VLAN_TAG     CPUPORT_BASE_ADDR + 0x0C

#define CPUPORT_INPUT_PORT_STATUS   CPUPORT_BASE_ADDR + 0x10
#define CPUPORT_WR_PKT_PM           CPUPORT_BASE_ADDR + 0x14
#define CPUPORT_WR_PKT_VLAN_TAG     CPUPORT_BASE_ADDR + 0x18
#define CPUPORT_WR_PKT_EGRS_RULE    CPUPORT_BASE_ADDR + 0x1C

#define CPUPORT_ALLOC_BUF_ADDR      CPUPORT_BASE_ADDR + 0x40
#define CPUPORT_LATCH_BUF_ADDR      CPUPORT_BASE_ADDR + 0x42
#define CPUPORT_BUF_ADDR0           CPUPORT_BASE_ADDR + 0x44
#define CPUPORT_BUF_ADDR1           CPUPORT_BASE_ADDR + 0x46
#define CPUPORT_BUF_ADDR2           CPUPORT_BASE_ADDR + 0x48
#define CPUPORT_DEQUE_ADDR0         CPUPORT_BASE_ADDR + 0x4C
#define CPUPORT_DEQUE_ADDR1         CPUPORT_BASE_ADDR + 0x4E


// PHY Control
#define PHYCTL_BASE_ADDR            0x0200

#define PHYCTL_ADDR_PORT_OFFSET     0x01
#define PHYCTL_OPER_PORT_OFFSET     0x01


#define PHYCTL_CMD_PORTID           PHYCTL_BASE_ADDR + 0x00
#define PHYCTL_REG_ADDR             PHYCTL_BASE_ADDR + 0x01
#define PHYCTL_WR_DATA              PHYCTL_BASE_ADDR + 0x02
#define PHYCTL_CMD                  PHYCTL_BASE_ADDR + 0x04
#define PHYCTL_STATUS               PHYCTL_BASE_ADDR + 0x08
#define PHYCTL_RD_DATA              PHYCTL_BASE_ADDR + 0x0A
#define PHYCTL_LINK_STATUS_CHANGE   PHYCTL_BASE_ADDR + 0x0C

#define PHYCTL_LINK_STATUS          PHYCTL_BASE_ADDR + 0x10
#define PHYCTL_BACK_PRESSURE_EN     PHYCTL_BASE_ADDR + 0x14
#define PHYCTL_FLOW_CTRL_ABL        PHYCTL_BASE_ADDR + 0x18
#define PHYCTL_FLOW_CTRL_ABL0_15    PHYCTL_BASE_ADDR + 0x18
#define PHYCTL_FLOW_CTRL_ABL16_25   PHYCTL_BASE_ADDR + 0x1C

#define PHYCTL_ADDR_BASE            PHYCTL_BASE_ADDR + 0x20

#define PHYCTL_AUTO_POLLING_EN      PHYCTL_BASE_ADDR + 0x3C

#define PHYCTL_OPER_CFG_BASE        PHYCTL_BASE_ADDR + 0x40

#define PHYCTL_PORT24_TBI_MODE      PHYCTL_BASE_ADDR + 0x60
#define PHYCTL_PORT24_INVLD_NUM     PHYCTL_BASE_ADDR + 0x61
#define PHYCTL_PORT25_TBI_MODE      PHYCTL_BASE_ADDR + 0x62
#define PHYCTL_PORT25_INVLD_NUM     PHYCTL_BASE_ADDR + 0x63
#define PHYCTL_PORT24_MODE_CFG      PHYCTL_BASE_ADDR + 0x68
#define PHYCTL_PORT25_MODE_CFG      PHYCTL_BASE_ADDR + 0x69
#define PHYCTL_DEFAULT_NWAY_CFG     PHYCTL_BASE_ADDR + 0x6C


// Forwarding Table Control
#define FWDCTL_BASE_ADDR            0x0300

#define FWDCTL_TBL_CFG              FWDCTL_BASE_ADDR + 0x00
#define FWDCTL_TBL_HASH             FWDCTL_BASE_ADDR + 0x02
#define FWDCTL_AUTO_AGE_CYCLE_TIME  FWDCTL_BASE_ADDR + 0x04
#define FWDCTL_AUTO_AGE_CFG         FWDCTL_BASE_ADDR + 0x07
#define FWDCTL_SOFT_AGE_CMD         FWDCTL_BASE_ADDR + 0x08
#define FWDCTL_AGE_INDEX            FWDCTL_BASE_ADDR + 0x0C
#define FWDCTL_AGE_STATUS           FWDCTL_BASE_ADDR + 0x0E

#define FWDCTL_CTRL_PKT_FWD_CFG     FWDCTL_BASE_ADDR + 0x10
#define FWDCTL_ARP_CFG              FWDCTL_BASE_ADDR + 0x12
#define FWDCTL_IP_CAP_CFG           FWDCTL_BASE_ADDR + 0x14
#define FWDCTL_IP_MCAST_CFG         FWDCTL_BASE_ADDR + 0x16
#define FWDCTL_VLAN_CFG             FWDCTL_BASE_ADDR + 0x18

#define FWDCTL_UCAST_FLOOD_DPM      FWDCTL_BASE_ADDR + 0x20
#define FWDCTL_L2_MCAST_FLOOD_DPM   FWDCTL_BASE_ADDR + 0x24
#define FWDCTL_IP_MCAST_FLOOD_DPM   FWDCTL_BASE_ADDR + 0x28
#define FWDCTL_BCST_DPM             FWDCTL_BASE_ADDR + 0x2C

#define FWDCTL_SWITCH_MAC_ADDR0     FWDCTL_BASE_ADDR + 0x30
#define FWDCTL_SWITCH_MAC_ADDR1     FWDCTL_BASE_ADDR + 0x34

#define CPUCTL_SWITCH_MAC_ADDR      FWDCTL_SWITCH_MAC_ADDR0

#define FWDCTL_LOOKUP_CFG0          FWDCTL_BASE_ADDR + 0x38
#define FWDCTL_LOOKUP_CFG1          FWDCTL_BASE_ADDR + 0x3A
#define FWDCTL_LOOKUP_CFG2          FWDCTL_BASE_ADDR + 0x3C
#define FWDCTL_LOOKUP_CFG3          FWDCTL_BASE_ADDR + 0x3E

#define FWDCTL_SNIFF_CFG            FWDCTL_BASE_ADDR + 0x40
#define FWDCTL_SNIFF_MODE           FWDCTL_BASE_ADDR + 0x42
#define FWDCTL_MIRROR_PORT_CFG      FWDCTL_BASE_ADDR + 0x44
#define FWDCTL_L2P_MIRROR_PORT_CFG  FWDCTL_BASE_ADDR + 0x44
#define FWDCTL_PRIORITY_MAP         FWDCTL_BASE_ADDR + 0x48
#define FWDCTL_PRIORITY_CFG         FWDCTL_BASE_ADDR + 0x4C
#define FWDCTL_PRIORITY_RAISED      FWDCTL_BASE_ADDR + 0x4E

#define FWDCTL_HASH_ARGU0           FWDCTL_BASE_ADDR + 0x50
#define FWDCTL_HASH_ARGU1           FWDCTL_BASE_ADDR + 0x54
#define FWDCTL_HASH_ARGU_FID        FWDCTL_BASE_ADDR + 0x56
#define FWDCTL_HASH_VALUE           FWDCTL_BASE_ADDR + 0x58
#define FWDCTL_INVS_HASH_ARGU0      FWDCTL_BASE_ADDR + 0x5C

#define FWDCTL_INVS_HASH_ARGU1      FWDCTL_BASE_ADDR + 0x60
#define FWDCTL_INVS_HASH_VALUE      FWDCTL_BASE_ADDR + 0x64
#define FWDCTL_LEARN_EN             FWDCTL_BASE_ADDR + 0x68
#define FWDCTL_SECURITY_DETECT_EN   FWDCTL_BASE_ADDR + 0x6C

#define FWDCTL_GBL_SECURITY_CFG     FWDCTL_BASE_ADDR + 0x70
#define FWDCTL_MISC_CFG             FWDCTL_BASE_ADDR + 0x74
#define FWDCTL_LOAD_BALANCE_ALG     FWDCTL_BASE_ADDR + 0x78
#define FWDCTL_SCAN_CMD_MV_FRM_FID  FWDCTL_BASE_ADDR + 0x7C
#define FWDCTL_SCAN_CMD_MV_FRM_PORT FWDCTL_BASE_ADDR + 0x7E
#define FWDCTL_SCAN_CMD_MV_TO_PORT  FWDCTL_BASE_ADDR + 0x7F

#define FWDCTL_SCAN_CMD             FWDCTL_BASE_ADDR + 0x80
#define FWDCTL_SCAN_STATUS          FWDCTL_BASE_ADDR + 0x84
#define FWDCTL_SEC_MAC_OWNER_CMD    FWDCTL_BASE_ADDR + 0x88

#define FWDCTL_LOG_CTRL             FWDCTL_BASE_ADDR + 0x90
#define FWDCTL_UNRD_READ_PTR        FWDCTL_BASE_ADDR + 0x94
#define FWDCTL_UNRD_WRITE_PTR       FWDCTL_BASE_ADDR + 0x96
#define FWDCTL_NUM_UNRD_ENTRY       FWDCTL_BASE_ADDR + 0x98
#define FWDCTL_NUM_PROC_ENTRY       FWDCTL_BASE_ADDR + 0x9C

#define FWDCTL_STP_STATE_PORT0_15   FWDCTL_BASE_ADDR + 0xA0
#define FWDCTL_STP_STATE_PORT16_25  FWDCTL_BASE_ADDR + 0xA4


// Initialization Control
#define INITCTL_BASE_ADDR           0x0400

#define INITCTL_CHIP_STRAP_CFG      INITCTL_BASE_ADDR + 0x00
#define INITCTL_EEP_WR_DATA         INITCTL_BASE_ADDR + 0x04
#define INITCTL_EEP_ADDR            INITCTL_BASE_ADDR + 0x05
#define INITCTL_EEP_CMD             INITCTL_BASE_ADDR + 0x06
#define INITCTL_EEP_RD_DATA         INITCTL_BASE_ADDR + 0x08
#define INITCTL_EEP_STATUS          INITCTL_BASE_ADDR + 0x0A
#define INITCTL_REVISION_ID         INITCTL_BASE_ADDR + 0x0C

#define INITCTL_BASIC_FUNC_CFG      INITCTL_BASE_ADDR + 0x14
#define INITCTL_LED_OUT_CFG         INITCTL_BASE_ADDR + 0x18
#define INITCTL_PAD_DELAY_CFG       INITCTL_BASE_ADDR + 0x1C

#define INITCTL_MAC_CFG             INITCTL_BASE_ADDR + 0x20
#define INITCTL_NORMAL_PKT_MAX_LEN  INITCTL_BASE_ADDR + 0x24
#define INITCTL_JUMBO_PKT_MAX_LEN   INITCTL_BASE_ADDR + 0x26
#define INITCTL_JUMBO_PKT_EN        INITCTL_BASE_ADDR + 0x28
#define INITCTL_TMAC_RESET          INITCTL_BASE_ADDR + 0x2C

#define INITCTL_EGRS_RATE_GBL_CFG   INITCTL_BASE_ADDR + 0x30
#define INITCTL_MIB_EN              INITCTL_BASE_ADDR + 0x34
#define INITCTL_YIF_SEL             INITCTL_BASE_ADDR + 0x38

#define INITCTL_POWER_UP_STATUS     INITCTL_BASE_ADDR + 0x40
#define INITCTL_POWER_UP_SOFT_TAG   INITCTL_BASE_ADDR + 0x44
#define INITCTL_POWER_UP_CMD        INITCTL_BASE_ADDR + 0x45


// Queue Control
#define QUECTL_BASE_ADDR            0x0500

#define QUECTL_OUT_SCHE_MODE        QUECTL_BASE_ADDR + 0x00
#define QUECTL_OUT_WEIGHT           QUECTL_BASE_ADDR + 0x04
#define QUECTL_DEQUE_CFG            QUECTL_BASE_ADDR + 0x08

#define QUECTL_OUT_SEL              QUECTL_BASE_ADDR + 0x40
#define QUECTL_OUT_HEAD_PTR         QUECTL_BASE_ADDR + 0x48
#define QUECTL_OUT_TAIL_PTR         QUECTL_BASE_ADDR + 0x4A
#define QUECTL_DEQUE_HOLD           QUECTL_BASE_ADDR + 0x4C


// Buffer Control
#define BUFCTL_BASE_ADDR            0x0600