inita.s

vt6528芯片交换机API函数和文档运行程序

/*
 * File:    inita.s for Cygwin
 *
 * Purpose: Initialization procedure for CPU.
 */


#include "devicea.S"




/*----------------------  Stack Definition  ----------------------------*/
/***************************************************/
    .section .DataSeg_Stack, "aw", %nobits
/***************************************************/

/* Stack memory section should starts immediately after the end of the
   BSS section */
    .align

    .space  STACK_SIZE_UND
STACK_UND:
    .space  STACK_SIZE_ABT
STACK_ABT:
    .space  STACK_SIZE_IRQ
STACK_IRQ:
    .space  STACK_SIZE_FIQ
STACK_FIQ:
    .space  STACK_SIZE_USR
STACK_USR:
    .space  STACK_SIZE_SVC
STACK_SVC:




/*----------------------  Static Definitions  --------------------------*/

/*----------------------  Static Macros  -------------------------------*/

/*----------------------  Static Variables  ----------------------------*/

/*----------------------  Export Variables  ----------------------------*/

/*----------------------  Export Functions  ----------------------------*/
    .global __main

/*----------------------  Import Variables  ----------------------------*/
    .extern _text_base                  /* Base of ROM code                     */
    .extern _text_end                   /* End of ROM code (=start of ROM data) */
    .extern _data_base                  /* Base of RAM to initialise            */
    .extern _bss_base                   /* Base of zero initialise RAM data     */
    .extern _bss_end                    /* Limit of zero initialise RAM data    */

/*----------------------  Import Functions  ----------------------------*/
    .extern Main_Entry

    .extern EISR_ExcptHndlr_Undef
    .extern EISR_ExcptHndlr_Prefetch
    .extern EISR_ExcptHndlr_Abort
    .extern EISR_ExcptHndlr_Irq
    .extern EISR_ExcptHndlr_Fiq




/***************************************************/
    .section .CodeSeg_Init, "ax"
/***************************************************/

/*---------------------------------------*/
/* Define entry point                    */
/*---------------------------------------*/
__main:                                 /* defined to ensure that C runtime system is not linked in */



/*---------------------------------------*/
/* (1). 1st Exception Handler Vector Entry Pointer (or setup vectors when ram at address 0) */
/*---------------------------------------*/
    /* Now fall into the {LDR PC, Reset_Addr} instruction which will continue
       execution at 'ExcptHndlr_System_Reset' */
ExcptHndlr_Vector_Init:
    LDR     pc, Reset_Addr
    LDR     pc, Undefined_Addr
    LDR     pc, SWI_Addr
    LDR     pc, Prefetch_Addr
    LDR     pc, Abort_Addr
    LDR     pc, Reserv_Addr
    LDR     pc, IRQ_Addr
    LDR     pc, FIQ_Addr

Reset_Addr:     .long   ExcptHndlr_System_Reset
Undefined_Addr: .long   ExcptHndlr_System_Undefined
SWI_Addr:       .long   ExcptHndlr_System_Swi
Prefetch_Addr:  .long   ExcptHndlr_System_Prefetch
Abort_Addr:     .long   ExcptHndlr_System_Abort
Reserv_Addr:    .long   ExcptHndlr_System_Reserv
IRQ_Addr:       .long   ExcptHndlr_System_Irq
FIQ_Addr:       .long   ExcptHndlr_System_Fiq


/* SYSTEM RESET: System Memory Initialize Data */
SystemMemInitDataOnReset:
    .long   rEXTDBWTH
    .long   rROMCON0
    .long   rROMCON1
    .long   rROMCON2
    .long   rROMCON3
    .long   rROMCON4
    .long   rROMCON5
    .long   rSDRAMCON0
    .long   rSDRAMCON1
    .long   rSDRAMCON2
    .long   rSDRAMCON3
    .long   rSREFEXTCON

/* SYSTEM REMAPPED: System Memory Initialize Data */
SystemMemInitDataOnRemapped:
    .long   rEXTDBWTH
    .long   maprROMCON0
    .long   maprROMCON1
    .long   rROMCON2
    .long   rROMCON3
    .long   rROMCON4
    .long   rROMCON5
    .long   maprSDRAMCON0
    .long   rSDRAMCON1
    .long   rSDRAMCON2
    .long   rSDRAMCON3
    .long   rSREFEXTCON


/*---------------------------------------*/
/* (3). 3rd Exception Handler Vector Entry Pointer (Consist of function call to C-Program) */
/*---------------------------------------*/
ExcptHndlr_System_Undefined:
    STMDB   sp!, {r0-r12,lr}
    MOV     r0, lr
    BL      EISR_ExcptHndlr_Undef
    LDMIA   sp!, {r0-r12,pc}^


ExcptHndlr_System_Swi:
    STMDB   sp!, {r0-r12,lr}
    LDR     r0, [lr, #-4]
    BIC     r0, r0, #0xFF000000
    CMP     r0, #0xFF
    BEQ     SwiCpuSetSVC
    CMP     r0, #0xFE
    BEQ     SwiCpuSetSYS
    LDMIA   sp!, {r0-r12,pc}^
/* SWI 0xFF: set CPU mode remain at SVC mode even when return */
SwiCpuSetSVC:
    MRS     r1, SPSR
    BIC     r1, r1, #MODE_MASK
    ORR     r2, r1, #SVC_MODE
    MSR     SPSR_cf, r2
    LDMIA   sp!, {r0-r12,pc}^
/* SWI 0xFE: set CPU mode remain at SYS mode even when return */
SwiCpuSetSYS:
    MRS     r1, SPSR
    BIC     r1, r1, #MODE_MASK
    ORR     r2, r1, #SYS_MODE
    MSR     SPSR_cf, r2
    LDMIA   sp!, {r0-r12,pc}^


ExcptHndlr_System_Prefetch:
    STMDB   sp!, {r0-r12,lr}
    MOV     r0, lr
    BL      EISR_ExcptHndlr_Prefetch
    LDMIA   sp!, {r0-r12,lr}
    SUBS    pc, lr, #4


ExcptHndlr_System_Abort:
    STMDB   sp!, {r0-r12,lr}
    MOV     r0, lr
    BL      EISR_ExcptHndlr_Abort
    LDMIA   sp!, {r0-r12,lr}
    SUBS    pc, lr, #8


ExcptHndlr_System_Reserv:
    B       ExcptHndlr_System_Reserv


ExcptHndlr_System_Irq:
    /* PATCH .... */
    STMDB   sp!, {r0}
    MRS     r0, SPSR
    TST     r0, #I_Bit                  /* If I bit = 1 (disable IRQ), exit */
    LDMIA   sp!, {r0}
    SUBNES  pc, lr, #4

    STMDB   sp!, {r0-r12,lr}
    BL      EISR_ExcptHndlr_Irq
    LDMIA   sp!, {r0-r12,lr}
    SUBS    pc, lr, #4


ExcptHndlr_System_Fiq:
    STMDB   sp!, {r0-r7,lr}
    BL      EISR_ExcptHndlr_Fiq
    LDMIA   sp!, {r0-r7,lr}
    SUBS    pc, lr, #4




/*---------------------------------------*/
/* The Reset Entry Point                 */
/*---------------------------------------*/
ExcptHndlr_System_Reset:


    MOV     r8, #0                      /* To setup SWI exception table address */
    ADRL    r9, ExcptHndlr_Vector_Init
                                        /* before we call SWI                   */
    LDMIA   r9!, {r0-r7}
    STMIA   r8!, {r0-r7}
    LDMIA   r9!, {r0-r7}
    STMIA   r8!, {r0-r7}

    SWI     0xFF                        /* When use ICE, set CPU mode to SVC mode */


    /*-----------------------------------*/
    /* disable IRQ/FIQ                   */
    /*-----------------------------------*/
    /* when reset, should had been at this mode,
       but we want to make sure */
    MRS     r0, CPSR
    ORR     r0, r0, #IFRQ_DISABLE
    MSR     CPSR_cf, r0

    /*-----------------------------------*/
    /* disable interrupt                 */
    /*-----------------------------------*/
    /* disable all interrupt */
    LDR     r1, =ASIC_INT_MASK
    LDR     r0, =MASK_ALL
    STR     r0, [r1]

    /* clear all pending interrupt */
    LDR     r1, =ASIC_INT_PEND
    LDR     r0, =PEND_CLSALL
    STR     r0, [r1]


    /*-----------------------------------*/
    /* Initialize STACK                  */
    /*-----------------------------------*/
    MRS     r0, CPSR
    BIC     r0, r0, #IFRQ_MASK | MODE_MASK
    ORR     r2, r0, #USR_MODE           /* r2 == USR mode, interrupt enable, for setup SPSR */

    /* set UND mode and set up stack pointer */
    ORR     r1, r0, #IFRQ_DISABLE | UND_MODE
    MSR     CPSR_cf, r1
    MSR     SPSR_cf, r2
    LDR     sp, =STACK_UND

    /* set ABT mode and set up stack pointer */
    ORR     r1, r0, #IFRQ_DISABLE | ABT_MODE
    MSR     CPSR_cf, r1
    MSR     SPSR_cf, r2
    LDR     sp, =STACK_ABT

    /* set IRQ mode and set up stack pointer */
    ORR     r1, r0, #IFRQ_DISABLE | IRQ_MODE
    MSR     CPSR_cf, r1
    MSR     SPSR_cf, r2
    LDR     sp, =STACK_IRQ

    /* set FIQ mode and set up stack pointer */
    ORR     r1, r0, #IFRQ_DISABLE | FIQ_MODE
    MSR     CPSR_cf, r1
    MSR     SPSR_cf, r2
    LDR     sp, =STACK_FIQ

    /* set SVC mode and set up stack pointer */
    ORR     r1, r0, #IFRQ_DISABLE | SVC_MODE
    MSR     CPSR_cf, r1
    MSR     SPSR_cf, r2
    LDR     sp, =STACK_SVC              /* now, return to SVC mode */


    /*-----------------------------------*/
    /* Exception Vector Table Setup      */
    /*-----------------------------------*/
    /* Otherwise we copy a sequence of LDR PC instructions over the vectors
       (Note: We copy LDR PC instructions because branch instructions
       could not simply be copied, the offset in the branch instruction
       would have to be modified so that it branched into ROM. Also, a
       branch instructions might not reach if the ROM is at an address
       > 32M). */
    MOV     r8, #0
    ADRL    r9, ExcptHndlr_Vector_Init
    LDMIA   r9!, {r0-r7}
    STMIA   r8!, {r0-r7}
    LDMIA   r9!, {r0-r7}
    STMIA   r8!, {r0-r7}


    /*-----------------------------------*/
    /* Initialize memory for C code      */
    /*-----------------------------------*/
    LDR     r0, =_text_end              /* Get pointer to ROM data                    */
    LDR     r1, =_data_base             /* and RAM copy                               */
    LDR     r3, =_bss_base              /* Zero init base => top of initialised data  */
    CMP     r0, r1                      /* Check that they are different              */
    BEQ     BSS_Clear
ROM_Vars_Loop:
    CMP     r1, r3                      /* Copy init data (RW data) from ROM space to RAM space */
    LDRCC   r2, [r0], #4
    STRCC   r2, [r1], #4
    BCC     ROM_Vars_Loop

BSS_Clear:
    LDR     r1, =_bss_end               /* Top of zero init segment */
    MOV     r2, #0
BSS_Loop:
    CMP     r3, r1                      /* Zero init the region from |Image$$ZI$$Base| */
    STRCC   r2, [r3], #4                /* to |Image$$ZI$$Limit|                       */
    BCC     BSS_Loop

    /*-----------------------------------*/
    /* Now change to user mode and set   */
    /* up user mode stack                */
    /* and enable IRQ/FIQ                */
    /*-----------------------------------*/
    MRS     r0, CPSR
    BIC     r0, r0, #IFRQ_MASK | MODE_MASK
    ORR     r0, r0, #USR_MODE
    MSR     CPSR_cf, r0
    LDR     sp, =STACK_USR

    /*-----------------------------------*/
    /* Now we enter the C Program        */
    /*-----------------------------------*/
    BL      Main_Entry




/*---------------------------------------*/
/* End of file                           */
/*---------------------------------------*/
    .end