📄 devicea.s
字号:
.equ DSX1, (2 << 22) /* EXTIO1 SWITCH == 16-bit width */
.equ DSX2, (1 << 24) /* EXTIO2 MODULE CARD == 8-bit width */
.equ DSX3, (0 << 26) /* EXTIO3 */
.equ rEXTDBWTH, DSR0+DSR1+DSR2+DSR3+DSR4+DSR5+DSD0+DSD1+DSD2+DSD3+DSX0+DSX1+DSX2+DSX3
/*---------------------------------------*/
/*-> ROMCON0 : ROM Bank0 Control register*/
/*---------------------------------------*/
.equ ROMBasePtr0, (ASIC_DRAM_BASE_ADDR >> 16) << 10
.equ ROMEndPtr0, ((ASIC_DRAM_BASE_ADDR+ASIC_ROM_0_SIZE) >> 16) << 20
.equ PMC0, 0x0 /* 0x0=Normal ROM, 0x1=4Word Page */
/* 0x2=8Word Page, 0x3=16Word Page */
.equ rTpa0, (0x0 << 2) /* 0x0=5Cycle, 0x1=2Cycle */
/* 0x2=3Cycle, 0x3=4Cycle */
.equ rTacc0, (0x4 << 4) /* 0x0=Disable, 0x1=2Cycle */
/* 0x2=3Cycle, 0x3=4Cycle */
/* 0x4=5Cycle, 0x5=6Cycle */
/* 0x6=7Cycle, 0x7=Reserved */
.equ rROMCON0, ROMEndPtr0+ROMBasePtr0+rTacc0+rTpa0+PMC0
.equ mapROMBasePtr0, (ASIC_ROM_BASE_ADDR >> 16) << 10
.equ mapROMEndPtr0, ((ASIC_ROM_BASE_ADDR+ASIC_ROM_0_SIZE) >> 16) << 20
.equ maprROMCON0, mapROMEndPtr0+mapROMBasePtr0+rTacc0+rTpa0+PMC0
/*---------------------------------------*/
/*-> ROMCON1 : ROM Bank1 Control register*/
/*---------------------------------------*/
.equ ROMBasePtr1, ((ASIC_DRAM_BASE_ADDR+ASIC_ROM_0_SIZE) >> 16) << 10
.equ ROMEndPtr1, ((ASIC_DRAM_BASE_ADDR+ASIC_ROM_0_SIZE+ASIC_ROM_1_SIZE) >> 16) << 20
.equ PMC1, 0x0 /* 0x0=Normal ROM, 0x1=4Word Page */
/* 0x2=8Word Page, 0x3=16Word Page */
.equ rTpa1, (0x0 << 2) /* 0x0=5Cycle, 0x1=2Cycle */
/* 0x2=3Cycle, 0x3=4Cycle */
.equ rTacc1, (0x4 << 4) /* 0x0=Disable, 0x1=2Cycle */
/* 0x2=3Cycle, 0x3=4Cycle */
/* 0x4=5Cycle, 0x5=6Cycle */
/* 0x6=7Cycle, 0x7=Reserved */
.equ rROMCON1, ROMEndPtr1+ROMBasePtr1+rTacc1+rTpa1+PMC1
.equ mapROMBasePtr1, ((ASIC_ROM_BASE_ADDR+ASIC_ROM_0_SIZE) >> 16) << 10
.equ mapROMEndPtr1, ((ASIC_ROM_BASE_ADDR+ASIC_ROM_0_SIZE+ASIC_ROM_1_SIZE) >> 16) << 20
.equ maprROMCON1, mapROMEndPtr1+mapROMBasePtr1+rTacc1+rTpa1+PMC1
/*---------------------------------------*/
/*-> ROMCON2 : ROM Bank2 Control register*/
/*---------------------------------------*/
.equ ROMBasePtr2, (0x380 << 10) /*=0x03800000 */
.equ ROMEndPtr2, (0x390 << 20) /*=0x03900000 */
.equ PMC2, 0x0 /* 0x0=Normal ROM, 0x1=4Word Page */
/* 0x2=8Word Page, 0x3=16Word Page */
.equ rTpa2, (0x0 << 2) /* 0x0=5Cycle, 0x1=2Cycle */
/* 0x2=3Cycle, 0x3=4Cycle */
.equ rTacc2, (0x4 << 4) /* 0x0=Disable, 0x1=2Cycle */
/* 0x2=3Cycle, 0x3=4Cycle */
/* 0x4=5Cycle, 0x5=6Cycle */
/* 0x6=7Cycle, 0x7=Reserved */
.equ rROMCON2, ROMEndPtr2+ROMBasePtr2+rTacc2+rTpa2+PMC2
/*---------------------------------------*/
/*-> ROMCON3 : ROM Bank3 Control register*/
/*---------------------------------------*/
.equ ROMBasePtr3, (0x390 << 10) /*=0x03900000 */
.equ ROMEndPtr3, (0x3A0 << 20) /*=0x03A00000 */
.equ PMC3, 0x0 /* 0x0=Normal ROM, 0x1=4Word Page */
/* 0x2=8Word Page, 0x3=16Word Page */
.equ rTpa3, (0x0 << 2) /* 0x0=5Cycle, 0x1=2Cycle */
/* 0x2=3Cycle, 0x3=4Cycle */
.equ rTacc3, (0x4 << 4) /* 0x0=Disable, 0x1=2Cycle */
/* 0x2=3Cycle, 0x3=4Cycle */
/* 0x4=5Cycle, 0x5=6Cycle */
/* 0x6=7Cycle, 0x7=Reserved */
.equ rROMCON3, ROMEndPtr3+ROMBasePtr3+rTacc3+rTpa3+PMC3
/*---------------------------------------*/
/*-> ROMCON4 : ROM Bank4 Control register*/
/*---------------------------------------*/
.equ ROMBasePtr4, (0x3A0 << 10) /*=0x03A00000 */
.equ ROMEndPtr4, (0x3B0 << 20) /*=0x03B00000 */
.equ PMC4, 0x0 /* 0x0=Normal ROM, 0x1=4Word Page */
/* 0x2=8Word Page, 0x3=16Word Page */
.equ rTpa4, (0x0 << 2) /* 0x0=5Cycle, 0x1=2Cycle */
/* 0x2=3Cycle, 0x3=4Cycle */
.equ rTacc4, (0x4 << 4) /* 0x0=Disable, 0x1=2Cycle */
/* 0x2=3Cycle, 0x3=4Cycle */
/* 0x4=5Cycle, 0x5=6Cycle */
/* 0x6=7Cycle, 0x7=Reserved */
.equ rROMCON4, ROMEndPtr4+ROMBasePtr4+rTacc4+rTpa4+PMC4
/*---------------------------------------*/
/*-> ROMCON5 : ROM Bank5 Control register*/
/*---------------------------------------*/
.equ ROMBasePtr5, (0x3B0 << 10) /*=0x03B00000 */
.equ ROMEndPtr5, (0x3C0 << 20) /*=0x03C00000 */
.equ PMC5, 0x0 /* 0x0=Normal ROM, 0x1=4Word Page */
/* 0x2=8Word Page, 0x3=16Word Page */
.equ rTpa5, (0x0 << 2) /* 0x0=5Cycle, 0x1=2Cycle */
/* 0x2=3Cycle, 0x3=4Cycle */
.equ rTacc5, (0x4 << 4) /* 0x0=Disable, 0x1=2Cycle */
/* 0x2=3Cycle, 0x3=4Cycle */
/* 0x4=5Cycle, 0x5=6Cycle */
/* 0x6=7Cycle, 0x7=Reserved */
.equ rROMCON5, ROMEndPtr5+ROMBasePtr5+rTacc5+rTpa5+PMC5
/*----------------------------------------*/
/*-> DRAMCON0 : RAM Bank0 control register*/
/*----------------------------------------*/
.equ DRAMBasePtr0, (ASIC_ROM_BASE_ADDR >> 16) << 10
.equ DRAMEndPtr0, ((ASIC_ROM_BASE_ADDR+ASIC_DRAM_SIZE) >> 16) << 20
.equ SRAS2CASDelay0, 1 /*(Trc)0=1cycle,1=2cycle */
.equ SRASPrechargeTime0, 1 /*(Trp)0=1cycle ~ 3=4clcyle */
.equ SNoColumnAddr0, 0 /*0=8bit,1=9bit,2=10bit,3=11bits */
.equ SCAN0, (SNoColumnAddr0 << 30)
.equ STrc0, (SRAS2CASDelay0 << 7)
.equ STrp0, (SRASPrechargeTime0 << 8)
.equ rSDRAMCON0, SCAN0+DRAMEndPtr0+DRAMBasePtr0+STrp0+STrc0
.equ mapDRAMBasePtr0, (ASIC_DRAM_BASE_ADDR >> 16) << 10
.equ mapDRAMEndPtr0, ((ASIC_DRAM_BASE_ADDR+ASIC_DRAM_SIZE) >> 16) << 20
.equ maprSDRAMCON0, SCAN0+mapDRAMEndPtr0+mapDRAMBasePtr0+STrp0+STrc0
/*----------------------------------------*/
/*-> DRAMCON1 : RAM Bank1 control register*/
/*----------------------------------------*/
.equ DRAMBasePtr1, (0x300 << 10) /*=0x03000000 */
.equ DRAMEndPtr1, (0x310 << 20) /*=0x03100000 */
.equ SRAS2CASDelay1, 1 /*(Trc)0=1cycle,1=2cycle */
.equ SRASPrechargeTime1, 1 /*(Trp)0=1cycle ~ 3=4clcyle */
.equ SNoColumnAddr1, 0 /*0=8bit,1=9bit,2=10bit,3=11bits */
.equ SCAN1, (SNoColumnAddr1 << 30)
.equ STrc1, (SRAS2CASDelay1 << 7)
.equ STrp1, (SRASPrechargeTime1 << 8)
.equ rSDRAMCON1, SCAN1+DRAMEndPtr1+DRAMBasePtr1+STrp1+STrc1
/*----------------------------------------*/
/*-> DRAMCON2 : RAM Bank2 control register*/
/*----------------------------------------*/
.equ DRAMBasePtr2, (0x310 << 10) /*=0x03100000 */
.equ DRAMEndPtr2, (0x320 << 20) /*=0x03200000 */
.equ SRAS2CASDelay2, 1 /*(Trc)0=1cycle,1=2cycle */
.equ SRASPrechargeTime2, 1 /*(Trp)0=1cycle ~ 3=4clcyle */
.equ SNoColumnAddr2, 0 /*0=8bit,1=9bit,2=10bit,3=11bits */
.equ SCAN2, (SNoColumnAddr2 << 30)
.equ STrc2, (SRAS2CASDelay2 << 7)
.equ STrp2, (SRASPrechargeTime2 << 8)
.equ rSDRAMCON2, SCAN2+DRAMEndPtr2+DRAMBasePtr2+STrp2+STrc2
/*----------------------------------------*/
/*-> DRAMCON3 : RAM Bank3 control register*/
/*----------------------------------------*/
.equ DRAMBasePtr3, (0x320 << 10) /*=0x03200000 */
.equ DRAMEndPtr3, (0x330 << 20) /*=0x03300000 */
.equ SRAS2CASDelay3, 1 /*(Trc)0=1cycle,1=2cycle */
.equ SRASPrechargeTime3, 1 /*(Trp)0=1cycle ~ 3=4clcyle */
.equ SNoColumnAddr3, 0 /*0=8bit,1=9bit,2=10bit,3=11bits */
.equ SCAN3, (SNoColumnAddr3 << 30)
.equ STrc3, (SRAS2CASDelay3 << 7)
.equ STrp3, (SRASPrechargeTime3 << 8)
.equ rSDRAMCON3, SCAN3+DRAMEndPtr3+DRAMBasePtr3+STrp3+STrc3
/*-------------------------------------------------------------------*/
/*-> REFEXTCON : External I/O & Memory Refresh cycle Control Register*/
/*-------------------------------------------------------------------*/
.equ ExtIOBase, (ASIC_EXTIO_BASE_ADDR >> 16) /*Ext IO base address */
.equ RefEnVSF, 0x18000 /*Refresh enable, VSF=1 */
.equ SRefCycle, 8 /*Unit [us], 4k refresh 64ms */
.equ ROWcycleTime, 3 /*0=1cycle, 1=2cycle, 2=3cycle, */
/*3=4cycle, 4=5cycle, */
.equ SRefCycleValue, (2048+1-(SRefCycle*fMCLK)) << 21
.equ STrc, ROWcycleTime << 17
.equ rSREFEXTCON, SRefCycleValue+STrc+RefEnVSF+ExtIOBase
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -