devicea.s

vt6528芯片交换机API函数和文档运行程序

/*
 * File:    devicea.S for cygwin
 */




/*************************************************************************/
/* Format of the Program Status Register                                 */
/*************************************************************************/
/*                                                                       */
/* 31  30  29   28         7   6   5   4   3   2   1   0                 */
/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+               */
/*| N | Z | C | V |      | I | F | T |     M4 ~ M0       |               */
/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+               */
/*                                                                       */
/* Processor Mode and Mask                                               */
/*                                                                       */
/*************************************************************************/

.equ    I_Bit,          0x80                /* IRQ disable                  */
.equ    F_Bit,          0x40                /* FIQ disable                  */
.equ    T_Bit,          0x20                /* Thumb state, read only       */
.equ    IFRQ_DISABLE,   0xC0                /* Interrupt disable mask value */
.equ    IFRQ_ENABLE,    0x00                /* Interrupt enable mask value  */
.equ    IFRQ_MASK,      0xC0                /* Interrupt lockout mask value */

.equ    UND_MODE,       0x1B                /* (UND) Undefine Mode       */
.equ    ABT_MODE,       0x17                /* (ABT) Abort Mode          */
.equ    SVC_MODE,       0x13                /* (SVC) Supervisor Mode     */
.equ    IRQ_MODE,       0x12                /* (IRQ) Interrupt Mode      */
.equ    FIQ_MODE,       0x11                /* (FIQ) Fast Interrupt Mode */
.equ    USR_MODE,       0x10                /* (USR) User Mode           */
.equ    SYS_MODE,       0x1F                /* (SYS) System Mode         */
.equ    MODE_MASK,      0x1F                /* Processor Mode Mask       */


/*------------------------------------------------------*/
/* Memory area layout definition                        */
/*------------------------------------------------------*/
.equ    ASIC_DRAM_BASE_ADDR,    0x00000000
.equ    ASIC_VEC_TBL_BASE_ADDR, 0x00F00000  /* limit addr of exception vector table */
.equ    ASIC_DRAM_SIZE,         0x01000000  /* size == 8MB x 2 == 16MB */

.equ    ASIC_ROM_BASE_ADDR,     0x01000000
.equ    ASIC_ROM_0_SIZE,        0x00400000  /* size == 4MB */
.equ    ASIC_ROM_1_SIZE,        0x00400000  /* size == 4MB */
                                            /* Although if when physically ROM0 is 512KB
                                               but we still configure it as 4MB anyway */

.equ    ASIC_EXTIO_BASE_ADDR,   0x03600000

.equ    ASIC_SRAM_BASE_ADDR,    0x03FE0000  /* Internal SRAM, size == 8KB */
                                            /* If not use cache, then we could
                                               use the cache ram as internal sram */


/*---------------------------------------*/
/* SYSTEM STACK MEMORY                   */
/*---------------------------------------*/
.equ    STACK_SIZE_UND,         512
.equ    STACK_SIZE_ABT,         512
.equ    STACK_SIZE_IRQ,         4096
.equ    STACK_SIZE_FIQ,         512
.equ    STACK_SIZE_SVC,         2048
.equ    STACK_SIZE_USR,         65536




/*------------------------------------------------------*/
/* SPECIAL REGISTERS : Start Address After System Reset */
/*------------------------------------------------------*/
.equ    ASIC_SOC_BASE_ADDR,     0x03FF0000


/* System Manager */
.equ    ASIC_SYS_SYSCFG,        ASIC_SOC_BASE_ADDR + 0x0000
.equ    ASIC_SYS_EXTDBWTH,      ASIC_SOC_BASE_ADDR + 0x3010


/* Interrupt Controller */
.equ    ASIC_INT_MODE,          ASIC_SOC_BASE_ADDR + 0x4000
.equ    ASIC_INT_PEND,          ASIC_SOC_BASE_ADDR + 0x4004
.equ    ASIC_INT_MASK,          ASIC_SOC_BASE_ADDR + 0x4008


/* I/O Port Interface */
.equ    ASIC_IOP_MOD,           ASIC_SOC_BASE_ADDR + 0x5000
.equ    ASIC_IOP_CON,           ASIC_SOC_BASE_ADDR + 0x5004
.equ    ASIC_IOP_DATA,          ASIC_SOC_BASE_ADDR + 0x5008


/* Timer 0, 1 */
.equ    ASIC_TMR_TMOD,          ASIC_SOC_BASE_ADDR + 0x6000
.equ    ASIC_TMR_TDATA0,        ASIC_SOC_BASE_ADDR + 0x6004
.equ    ASIC_TMR_TDATA1,        ASIC_SOC_BASE_ADDR + 0x6008
.equ    ASIC_TMR_TCNT0,         ASIC_SOC_BASE_ADDR + 0x600C
.equ    ASIC_TMR_TCNT1,         ASIC_SOC_BASE_ADDR + 0x6010




/* Bits in the ASIC_INT_PEND register */
.equ    PEND_CLSALL,            0x001FFFFF


/* Interrupt vector for each device */
.equ    VEC_EXT0_INT,           0
.equ    VEC_EXT1_INT,           1
.equ    VEC_EXT2_INT,           2
.equ    VEC_EXT3_INT,           3
.equ    VEC_UART0_TX_INT,       4
.equ    VEC_UART0_RX_ERR_INT,   5
.equ    VEC_UART1_TX_INT,       6
.equ    VEC_UART1_RX_ERR_INT,   7
.equ    VEC_GDMA2_INT,          8
.equ    VEC_GDMA1_INT,          9
.equ    VEC_TIMER0_INT,         10
.equ    VEC_TIMER1_INT,         11
.equ    VEC_HDLC_A_TX_INT,      12
.equ    VEC_HDLC_A_RX_INT,      13
.equ    VEC_HDLC_B_TX_INT,      14
.equ    VEC_HDLC_B_RX_INT,      15
.equ    VEC_BDMA_TX_INT,        16
.equ    VEC_BDMA_RX_INT,        17
.equ    VEC_MAC_TX_INT,         18
.equ    VEC_MAC_RX_INT,         19
.equ    VEC_I2C_INT,            20


/* Bits in the ASIC_INT_MASK register */
.equ    MASK_ALL,               0x003FFFFF




/*----------------------------------------*/
/* SYSTEM CLOCK (for DRAM refresh & UART) */
/*----------------------------------------*/
/* NOTE: The System Clock is a 10 MHz Oscillator
         feeding a PLL that generates 50 MHz fMCLK) internally!
         The Timer Divider value is based on that 50 MHz rate, using the
         following: Timer Unit 10 ms (.010) times the fMCLK (50000000)
         gives: 500000 -1 = 499999 -- Hex 0x0007A11F !  This is the value
         loaded into Timer0's Data register
*/
.equ    fMCLK_MHz,          50000000
.equ    MHz,                1000000
.equ    fMCLK,              (fMCLK_MHz / MHz)


/*---------------------------------------*/
/* SYSCFG : System configuration register*/
/*---------------------------------------*/
.equ    SDM,                (1 << 31)                           /* SDRAM Mode, 0=EDO DRAM, 1=SDRAM */
.equ    PD_ID,              (1 << 26)                           /* S3C4510X=00001 */
.equ    S_REG_BASE_PTR,     (ASIC_SOC_BASE_ADDR >> 16) << 16    /* Special register bank base pointer */
.equ    I_SRAM_BASE_PTR,    (ASIC_SRAM_BASE_ADDR >> 16) << 6    /* Internal SRAM base pointer */
.equ    CM,                 (1 << 4)                            /* Cache Mode, 0=4K sram 4K cache, 1=8K cache, 2=8K sram */
.equ    WE,                 (1 << 2)                            /* Write buffer Enable, 0=disable, 1=enable */
.equ    CE,                 (1 << 1)                            /* Cache Enable, 0=disable, 1=enable */
.equ    SE,                 (0 << 0)                            /* Stall Enable, must be 0 */

.equ    SYSCFG_INIT_VAL,    SDM + PD_ID + S_REG_BASE_PTR + I_SRAM_BASE_PTR + CM + WE + CE + SE


/*-------------------------------------*/
/* EXTDBWTH : Memory Bus Width register*/
/*-------------------------------------*/
/* 0 : Disable
 * 1 : Byte 8-bit
 * 2 : Half-Word 16-bit
 * 3 : Word 32-bit
 */
.equ    DSR0,           (2 << 0)            /* ROM0      Flash ROM0 == 16-bit width
                                                         ROM0 data width actually connot be configured,
                                                         is decided by jumper strapping */
.equ    DSR1,           (2 << 2)            /* ROM1      Flash ROM1 == 16-bit width */
.equ    DSR2,           (0 << 4)            /* ROM2 */
.equ    DSR3,           (0 << 6)            /* ROM3 */
.equ    DSR4,           (0 << 8)            /* ROM4 */
.equ    DSR5,           (0 << 10)           /* ROM5 */
.equ    DSD0,           (3 << 12)           /* DRAM0     SDRAM == 32-bit width */
.equ    DSD1,           (0 << 14)           /* DRAM1 */
.equ    DSD2,           (0 << 16)           /* DRAM2 */
.equ    DSD3,           (0 << 18)           /* DRAM3 */
.equ    DSX0,           (0 << 20)           /* EXTIO0 */